A couple weeks ago I started trying to consolidate a list of all the ways one could usefully use 1-3 logic ICs in a discrete logic mapper. I thought I'd post the list here to see if it inspires some other ideas.
Without further ado:
Do you have any other ideas?
edit: add link to tepples's 74'670 quad-banked design
edit: some new ideas
Without further ado:
- 1 IC
- Anything usable as an inverter, such as (⅙ 7404, 05, 06, 07, 14, 16, 19, ¼ 7400, 01, 02, 03, 24, 25, 26, 28, 33, 36, 37, 38, 39, 86, ⅓ 7410, 12, 27, ½ 7413, 18, 20, 22, 23, 25, 40)
→ Avoids bus conflicts on bankswitch writes by making ROM /OE ← NOT R/W - Selecting logic such as 7420, 138, 139
→ Add up to 8KiB WRAM mapped from $6000-$7fff
→ (138, ½ 139) Split 32KiB into 16KiB RAM from $8000-$BFFF and 16KiB ROM from $C000-$FFFF - 7485 (4-bit comparator)
→ Map up to 46KiB from $4800-$FFFF
→ Map up to 44KiB from $5000-$FFFF without bus conflicts - 7486 (quad XOR)
→ Double effective CHR with a palette reordering of tiles by e.g. making CHR(A3) ← PPU(A11) XOR PPU(A3) (swaps colors 1 and 2).
→ Double effective CHR with a vertical flip by making CHR(A0,A1,A2) ← PPU(A11) XOR PPU(A0,A1,A2). - Any latch with an active-low clock enable, such as 74161, 74377
→ Most of Nintendo's discrete-logic mappers (AxROM, BNROM, CNROM, GNROM, MHROM)
→ Arbitrary GNROM-style mappers with 32KiB PRG banks and 8KiB CHR banks
→ Mapper-controlled 1-screen mirroring (a la AxROM)
→ Oeka Kids-style dynamic banking of CHR with zones as small as the size of an attribute byte (32x32 pixel), by connecting Latch./CLKEN ← /PPUA13 and Latch.CLK ← /RD
→ Additionally, a simple circuit (diode, resistor, capacitor) can automatically clear a 161 on reset - Any sufficiently large binary counter, such as (74)4020
→ Interrupts for 2ⁿ X every 2⁽ⁿ⁺¹⁾ X, where X could be (A12 rises = scanlines·8, cpu cycles, PPU reads) - Tristatable dual 4-input multiplexer (74'253) in lieu of CHR ROM, plus 8 ≈1kΩ resistors (or a 74244):
→ Game Genie style low-resolution graphics, where each 4-by-4 pixel zone is individually controllable and can have any color D3…D0←SEL(A3…A2,A11…A8) and D7…D4←SEL(A3…A2,A7…A4) - 74'153 or 74'157, plus 8 ≈1kΩ resistors (or a 74244): (added 2013-III-10)
→ Allow selective disabling of 1kB NT RAM so-as-to split bitplanes. CIRAM/SEL ← SEL(A3,A10,A11), SEL/E ← A13, D0…D7 ← A12 through resistors or buffer
- Anything usable as an inverter, such as (⅙ 7404, 05, 06, 07, 14, 16, 19, ¼ 7400, 01, 02, 03, 24, 25, 26, 28, 33, 36, 37, 38, 39, 86, ⅓ 7410, 12, 27, ½ 7413, 18, 20, 22, 23, 25, 40)
- 2 ICs
- Any obsolete RAM such as 74170, 670, 189, 219, 289 plus decoding logic (7432) :
→ 4 (for the two 74?70) or 16 (for the three 74??9) independently controlled banks. - 7485 + 74(4078) (comparator+8-input NOR)
→ Map almost 48KiB from $4020-$FFFF without bus conflicts - Any latch plus decoding logic, such as 7400, 02, 32, 133, 138 + 7474, 173, 174, 176
→ GNROM-style mappers as made by not-Nintendo - Timer/counter plus decoding logic, such as 7400 + 555/(74)4020/74123
→ Acknowledgable interrupts - Two multiplexers forming an eight-of-sixteen multiplexer (2× 74157)
→ Double effective CHR with a horizontal flip of tiles by making PPU(D0…D7) ← SELECT(PPU(A11),CHR(D0…D7),CHR(D7…D0)) - Eight XOR gates (2x 7486) added 2012-IX-6
→ Double effective CHR with a palette inversion (3↔0, 1↔2) by making PPU(D0…D7) ← CHR(D0…D7) XOR A11 - Any latch with an active-low clock enable plus:
- Masking logic, such as 7400, 02, 08, 32
→ UxROM and similar with a fixed bank of PRG or CHR - Inverting masking logic, such as 7400, 02 (added 2013-V-2)
→ UxROM without bus conflicts and similar with a fixed bank of PRG or CHR (max 3 bits of banking) - a quad 1-of-2 multiplexer (74157)
→ Two independently controllable banks
→ Two independently controllable banks and two duplicate fixed banks - Tristatable quad 1-2 multiplexer (74'257) and four >1kΩ resistors (refinement of previous, added 2013-V-12)
→ Two independently controllable banks and two different fixed banks (128kiB PRG example: Three resistors pull ROM A14..A16 high. The last connects CPU A13→ROM A13 but can be overridden by the mux) - ½ dual 1-of-4 multiplexer (74153)
→ Controllable horizontal/vertical/1screen mirroring - A single 1-of-2 multiplexer (7400)
→ Controllable horizontal/vertical mirroring (as used by Holy Diver)
- Masking logic, such as 7400, 02, 08, 32
- Inverter (such as 7400, 7404, 7486) + 8KB RAM added 2012-IX-6
→Map 8KB RAM into PPU $0xxx and $2xxx for 4KB CHR-RAM slice and 4-screen mirroring, inverter makes NOT A12 to decode 4KB ROM (or 4KB window) in $1xxx
- Any obsolete RAM such as 74170, 670, 189, 219, 289 plus decoding logic (7432) :
- 3 ICs
- Latch, Logic, quad 1-of-2 multiplexer added 2012-IX-6
→ Split CPU or PPU space into 2ⁿ moving and (the rest) fixed bank. e.g. using a 7408: Make PPU $0000-$17FF fixed with a 2KB bank at $1800-$1FFF by SEL←PPUA12 AND PPUA11 and using the multiplexer to either pass 0,0,A12,A11 to the CHR or the latched value.
- Latch, Logic, quad 1-of-2 multiplexer added 2012-IX-6
Do you have any other ideas?
edit: add link to tepples's 74'670 quad-banked design
edit: some new ideas