nes cpu-memory timing diagrams

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nes cpu-memory timing diagrams
by krzysiobal on 2011-06-12 (#79585)
Hello,
I have a few technical questions about cpu-memory timing diagrams in nes.

First of all - why the PRG-SEL line is the CPU-ADR15 line and-ed with the cpu clock, so it is high only when the cpu clock is hight and addres = 0x8000-0xFFFF ? (the same is for the lines connected to cs in prg-ram and ppu-cs). Is it a kind of protection to make the one device (ppu, prg-ram, prg-rom) pull data lines to high-z before other device puts data on it? Would it work when PRG-SEL would be just CPU-ADDR15?

The second is about NROM. I've found a schematics to it.
http://atariusa.com/Famicom_Schematics/ ... ematic.png

Image

I hope is it right.

First of all - why the /ROMSEL is connected to /OE and VCC to /CE in PRG-ROM and not vice-versa? Does the memory reacts faster on OE that on CE?

The second is about CHR-ROM - why do both lines needs to be connected - PA13 to /CS and /RD to /OE? Will it work when PA13 is connected to /CS and /OE to VCC?
Re: nes cpu-memory timing diagrams
by lidnariq on 2011-06-12 (#79589)
krzysiobal wrote:
First of all - why the PRG-SEL line is the CPU-ADR15 line and-ed with the cpu clock, so it is high only when the cpu clock is hight and addres = 0x8000-0xFFFF ? (the same is for the lines connected to cs in prg-ram and ppu-cs). Is it a kind of protection to make the one device (ppu, prg-ram, prg-rom) pull data lines to high-z before other device puts data on it? Would it work when PRG-SEL would be just CPU-ADDR15?
It makes cartridges cheaper by not needing include a extra IC on every game. (Why did they not include A15, M2, and /PRGSEL ? Compatibility with the famicom, but why it wasn't on the famicom? Dunno.) It would not work to just use A15 because of setup and hold times.
Quote:
First of all - why the /ROMSEL is connected to /OE and VCC to /CE in PRG-ROM and not vice-versa? Does the memory reacts faster on OE that on CE?
Exactly.
Quote:
The second is about CHR-ROM - why do both lines needs to be connected - PA13 to /CS and /RD to /OE? Will it work when PA13 is connected to /CS and /OE to VCC?
It's a way of avoiding bus conflicts so that if you wrote to CHRROM nothing bad could happen. *EDIT: You can't ignore /RD, the moment before is an "ALE cycle" when the device is loading the lower 8 bits of address over the data bus. /RD tells you that the bus is now free from contention.
Re: nes cpu-memory timing diagrams
by qbradq on 2011-06-13 (#79624)
Some clarifications:

krzysiobal wrote:
Hello,
First of all - why the PRG-SEL line is the CPU-ADR15 line and-ed with the cpu clock, so it is high only when the cpu clock is hight and addres = 0x8000-0xFFFF ?


PRG /CE is PRG A15 NAND M2, so PRG /CE is low only when PRG A15 and M2 are high.

krzysiobal wrote:
First of all - why the /ROMSEL is connected to /OE and VCC to /CE in PRG-ROM and not vice-versa?


The PRG-ROM chip's /CE line is tied to Ground. Vss is a Ground pin.