TLSROM, the board used by NES Play Action Football, Goal II and Pro Sport Hockey seems to be especially difficult for modern emulators to emulate correctly. I was curious enough to procure a cart of one of these games to see whether there was a reason why. Looking at the board I cannot find one. It looks exactly the same as a TLROM board, the vanilla MMC3 board. No extra V-RAM like TVROM, TR1ROM and DRROM (Rad Racer II and Gauntlet) or CHR-RAM like TQROM (Pinbot and High Speed) or even W-RAM like TSROM or TKROM. Does the TLSROM, which does have some different traces from TLROM, change the intended functionality of the MMC3 in some way? (Consider SUROM which allowed Dragon Warriors III and IV to have 512KB of PRG-ROM when the MMC1 only supported half that using the CHR banking lines.) Or do these games require some timing critical MMC3 functionality that earlier emulators could not emulate and so made up a new mapper to simulate the functionality? (Wouldn't be the first time either.)
TLSROM switches mirroring based on D7 of CROM bank selection, otherwise it's just like TLROM, I think. Not sure, though.
This 'mirroring switch' is EXTREMELY simple to emulate, once you figure out exactly what is going on.
* The upper CHR line goes straight to VRAM A10.
* The MMC3 does not monitor PPU A13.
-> The MMC3 outputs the same CHR bank values for $2000-$3FFF as for $0000-$1FFF.
--> The CHR banks mapped at $0000-$0FFF will directly determine the nametables visible at $2000-$2FFF.
The result is much more precise control over mirroring than the MMC3 would normally allow, at the cost of one CHR address line (and putting the 2KB switchable banks at $1000-$1FFF).
Some emulators handle this in a really odd way, by monitoring all PPU accesses and setting 1-screen mirroring based on the last address accessed. The proper way to do it is similar to the way one would normally handle MMC5 mirroring - set specific nametables at each memory region, based on the CHR banks mapped at $0000-$0FFF.
Quietust wrote:
* The upper CHR line goes straight to VRAM A10.
* The MMC3 does not monitor PPU A13.
*doh*
Indeed, once you put it that way, it's all really obvious
Thanks!
Ok. I try modifi SMB2 cartridge to YS3e TLSROM. Without any modification YS3e display this gfx/mirroring bugs:
http://members.lycos.co.uk/siudym/ys3bug1.avi
I cut connection from cart conn. CHR A10 to MMC3 and CHR ROM A10 from MMC3. And i connect directly A10 from conn. to CHROM. Now ingame graphics are good: (vert. scrolling are good)
http://members.lycos.co.uk/siudym/ys3gut2.avi
BUT NOW, i found another gfx errors, only in levels with Vertical Screen Scrolling:
http://members.lycos.co.uk/siudym/ys3e_v.avi
How to fix it???
I have no idea...
Are you sure the mirroring connection is set up right? The MMC3 should have a "CIRAM A10" pin which controls the PPU mirroring. A TLSROM board probably doesn't have the pin connected to anything, so make sure that pin goes to the CIRAM A10 pin on the cart edge.
ok. i cut connection cart CIRAM A10->MMC3 and.... i see grey/black screen:/
I must leave conn. CIRAM A10 NC? or connect to somewhere?
I have also leave NC MMC3 pins: CHR A10 (rom) , CHR A10 (C) and CIRAM A10 (C).
CIRAM A10 actually connects to one of the MMC3's CHR bank pins.
but where precisely?