Recently I've been designing parts of the 6502 to eventually synthesize, but I couldn't help but wonder how the CPU is actually implemented. I recently stumbled across this page: http://impulzus.sch.bme.hu/6502/letolt.php3
It contains reverse engineered transistor level schematics of a R6502!
This page gives an overview of how NMOS gates are constructed:
http://homepages.ius.edu/JFDOYLE/c421/html/Chapter3.htm
What it doesn't cover is that the transistors can be made into resistors as shown here: http://www.ececs.uc.edu/~dpl/vishwa_thesis/node77.html
Anyone wanna help me translate the diagram into logic gates (where applicable)? Some liberties must be taken to turn it into a static design.
I have converted the Postscript to a really big (over 7000x7000 pixels / 300kb) PNG file I can hopefully upload to Imageshack if anyone is interested.
It contains reverse engineered transistor level schematics of a R6502!
This page gives an overview of how NMOS gates are constructed:
http://homepages.ius.edu/JFDOYLE/c421/html/Chapter3.htm
What it doesn't cover is that the transistors can be made into resistors as shown here: http://www.ececs.uc.edu/~dpl/vishwa_thesis/node77.html
Anyone wanna help me translate the diagram into logic gates (where applicable)? Some liberties must be taken to turn it into a static design.
I have converted the Postscript to a really big (over 7000x7000 pixels / 300kb) PNG file I can hopefully upload to Imageshack if anyone is interested.