I'm not sure if anyone could use this but here's a basic DRAM circuit for 6502:
It does 1 hidden refresh cycle per read/write, if you use a faster clock you can get in more refresh cycles by altering it to toggle /RAS after /RAS = 1 && /CAS = 0
Adjust the NAND gate for the JKFF's CLK active level
It does 1 hidden refresh cycle per read/write, if you use a faster clock you can get in more refresh cycles by altering it to toggle /RAS after /RAS = 1 && /CAS = 0
Adjust the NAND gate for the JKFF's CLK active level