Kaiser chips KS204/KS203/KS202 + kaiser boards

Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243129)
After some testing and checking of Kaiser chips and boards I think it is a good time to sum up my current state of knowledge.

Chips

KS204
Image
Code:
             .--\/--.                                     .--\/--.           
       M2 -> |01  28| -- +5V                        M2 -> |01  28| -- +5V   
      R/W -> |02  27| <- RESET                     R/W -> |02  27| <- RESET 
  CPU A14 -> |03  26| <- CPU D3             CPU A14/D3 -> |03  26| -> CHR A16
  CPU A13 -> |04  25| -> CHR A15            CPU A13/D2 -> |04  25| -> CHR A15
   CPU D1 -> |05  24| -> CHR A14            CPU A12/D1 -> |05  24| -> CHR A14
   CPU D0 -> |06  23| -> CHR A13            CPU A1 /D0 -> |06  23| -> CHR A13
  /ROMSEL -> |07  22| -> CHR A12               /ROMSEL -> |07  22| -> CHR A12
   CPU D4 -> |08  21| -> CHR A11       (unused) CPU D4 -> |08  21| -> CHR A11
   CPU A0 -> |09  20| -> CHR A10                CPU A0 -> |09  20| -> CHR A10
  PRG A16 <- |10  19| <- CPU D5                PRG A16 <- |10  19| -> CIR-A10
  PRG A15 <- |11  18| <- PPU A12               PRG A15 <- |11  18| <- PPU A12
  PRG A14 <- |12  17| <- PPU A11               PRG A14 <- |12  17| <- PPU A11
  PRG A13 <- |13  16| <- PPU A10               PRG A13 <- |13  16| <- PPU A10
      GND -- |14  15| <- CPU D2                    GND -- |14  15| -> PRG /CE (0 when /ROMSEL=0 and R/W=1 else 1)
             '------'                                     '------'           
              KS 204                                       KS 204
           in MMC3 mode                                 in VRC2 mode

This chip can act either as simplified MMC3 or VRC2.

MMC3 mode:
* Enabled when M2 is high when chip is during RESET
* Chip behaves like simplified MMC3 (http://wiki.nesdev.com/w/index.php/INES_Mapper_206)
* Writes to internal regs occurs neither on falling edge of M2, rising edge of /ROMSEL, but on rising edge of its internal clock signal, for example:
Code:
CLK_8000 <= '0' when /ROMSEL = 0 and M2 = 1 and R/W = 0 and A1 = 0 and A14 = 0 and A13 = 0 else '1'

* Metroid (FDS Conversion) (KS-7037) wired it a little differently and used only its PRG registers

VRC2 mode:
* Enabled when M2 is low when chip is during RESET
* During rising edge of M2, signals on pins 3-6 are latched internally as A14/A13/A12/A1
* During falling edge of M2, if /ROMSEL is 0 and R/W is 0 then a write to internal register occurs with
previously latched A14/A13/A12/A1 + current value of A0 + current values of pins3-6 (which are treaten as D3/D2/D1/D0)
* The value of pin 8 (D4) does not seem to have any influence on PRG/CHR/CIRAM operation (and there is no CHR-A18/PRG-A17), however Gyruss still wires it.
* Gyruss (FDS Conversion) (KS-7057) wired it differently and user only its CHR registers (for controlling PRG banks!)
* Contra J (KS-7049) probably used it in its natural way (that would explain presence of 74LS157 for muxing pins3-6 + 7432 for CHR /CE)

--------------------------------------------------------------------------------

KS203
Image
Code:
              .--\/--.
   PRG A17 <- |01  24| <- PPU A10
   PRG A16 <- |02  23| <- PPU A11
   PRG A15 <- |03  22| <- PPU A12
   PRG A14 <- |04  21| <- CPU A13
       VCC -- |05  20| <- CPU A14
   PRG /CE <- |06  19| <- /ROMSEL
   CHR A12 <- |07  18| <- RESET
   CHR A13 <- |08  17| -- GND
    CPU D7 -> |09  16| <- M2
    CPU D0 -> |10  15| <- CPU R/W
   CHR A16 <- |11  14| -> CHR A15
   CIR A10 <- |12  13| -> CHR A14
              '------'
               KS 203

This chip can acts like MMC1. Further testing is required to see if there are any hidden functions.
* Rockman 2 - Dr Wily no Nazo (J) (KS-7061) used only its PRG registers

--------------------------------------------------------------------------------

KS202
Image
Code:
                .--\/--.
     CPU-A12 -> |01  20| -> WRAM-/CE
     CPU-A13 -> |02  19| <- CPU-D3
     CPU-A14 -> |03  18| <- CPU-R/W
         VCC -- |04  17| <- CPU-D0
          M2 -> |05  16| <- CPU-D1
     PRG-A14 <- |06  15| <- CPU-D2
     PRG-A13 <- |07  14| -- GND
     PRG-A15 <- |08  13| <- CPU-/ROMSEL
     PRG-A16 <- |09  12| <- RESET
     PRG-/CE <- |10  11| -> /IRQ
                '------'
                 KS 202

This chip acts like VRC3.
* Super Mario Bros 3 used it.
* Super Mario Bros 2 J - The Lost Levels used it.
* Salamander might use it

--------------------------------------------------------------------------------

Kaiser boards:
*KS-7010: Game: ?, Mapper: KS7010
*KS-7012: Game: Zanac (FDS Conversion), Mapper: KS7012 / 346
*KS-7013: Game: Highway Star, Mapper: KS7013 / 312
*KS-7016: Game: Exciting Basket (FDS Conersion), Mapper: KS7016 / 306
*KS-7017: Game: Almana no Kiseki (FDS Conversion), Mapper: KS7017 / 303
*KS-7021: Game: Contra , Mapper: 525
*KS-7030: Game: Doki Doki Panic (FDS Conversion), Mapper: KS7030 / 347
*KS-7031: Game: Dracula II: Noroi no Fūin (FDS Conversinon), Mapper: KS7031 / 305
*KS-7032: Game: Super Mario Bros 2 Lost Levels, Mapper: KS7032 / 142
*KS-7037: Game: Metroid (FDS Conversion), Mapper: KS7037 / 307
*KS-7041: Game: 20 in 1
Image Image Image Image Image
*KS-7049: Game: Contra J, Mapper: 23
*KS-7057: Game: Gyruss (FDS Conversion), KS7057 / 302
*KS-7058: Game: ?, Mapper: 171
*KS-7061: Game: : Rockman 2 - Dr Wily no Nazo (J), Mapper: 1
Re: Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243131)
krzysiobal wrote:
KS202
[...]* Super Mario Bros 3 used it.
* Super Mario Bros 2 J - The Lost Levels used it.
* Salamander might use it
GoodNES additionally has a "Bubble Bobble (FDS Conversion) (Unl).nes" (mapper 142) and "Bubble Bobble (FDS Conversion) (Unl) [U][!].nes" (UNIF UNL-KS7032); either way PRG CRC32 is 0x96defabe.

It unfortunately also has a "Pipe 5 (Sachen) [!].nes" (PRG CRC32 0x5a643d92) marked as mapper 142, but it has more than 8KB of CHR and Nestopia's database patches the header to mapper 79.
Re: Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243133)
KS7010A==KS7010,A is TTL
KS7008== Green Beret (Unl) (FDS Conversion)
kS7009==Family Boxing (Kaiser)(KS7009,Unl) Clone
KS7013B == Highway Star (Kaiser)
KS7015 == VRC3
KS7016A=KS7016,
KS7019 = Falsion (FDS Conversion, Kaiser)
KS7035 = UxROM
KS7001BH = NROM,super mario
Re: Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243138)
KS7001 for NROM games (observed in a LB35 copy).
Re: Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243166)
I still had some doubts about how the KS204 recognizes in which mode it is switched. The way I described it above worked for switching it once after power up, but then changing the mode again didn't work until next power-up.

What I found odd is that Metroid (MMC3 mode) pulls pin 3 down through 4.7k, while Gyruss (VRC2 mode) pulls M2 down through 1.5k, while .
Pin 27 is certainly reset, because both games have it wired to RC ciruit.
Code:
             .--\/--.                                     .--\/--.           
       M2 -> |01  28| -- +5V                        M2 -> |01  28| -- +5V   
      R/W -> |02  27| <- RESET                     R/W -> |02  27| <- RESET
  CPU A14 -> |03  26| <- CPU D3             CPU A14/D3 -> |03  26| -> CHR A16
                ..                                           ..
             '------'                                     '------'           
              KS 204                                       KS 204
           in MMC3 mode                                 in VRC2 mode 
          (Metroid)                                      (Gyruss)

What I also accidentally observed is that when M2 is low, KS204's RESET seems to be internally shorted to GND because applying 5V to it (through 1k) does not change logic level on this pin. Only when M2 is high, RESET is possible.

Assuming that the KS204's reset is faster than CPU's reset (otherwise it won't work at all)
Code:
                    Metroid                                   Gyruss
VCC         ___-----------------------------  ___-----------------------------
KS204'reset ___----------___________________  ________________________________
CPU's reset _____________________-----------  _____________________-----------
M2          ___------------------_-_-_-_-_-   ______________________-_-_-_-_-
pin3        ______________________-_-_-_-_-   ______________________-_-_-_-_-

Metroid, leaving M2 to be pulled up (by the 74139 inside console or inside cartridge), allows reset and pulling pin 3 down puts it in MMC3 mode.

Gyruss, by pulling M2 down, forbids reseting the chip and let the chip stays in his default power-up mode (VRC2)

After doing test, I confirm that during RESET, pin 3 can control if it will work as VRC2 (VCC) or MMC3 (low), so the chip can be switched even in run-time.

Any combination on other input pins during reset does not matter, so there are no more `hidden` modes.
Re: Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243182)
I did more testing to he KS203 chip. It also seems to have 2 modes: MMC1 and non-MMC1. Switching between them works exactly the same like in KS204 (here - pin 20 decides: VCC=MMC1, GND=non-MMC1)

Code:
              .--\/--.                               .--\/--.
   PRG A17 <- |01  24| <- PPU A10        /PPU A11 <- |01  24| <- PPU A10
   PRG A16 <- |02  23| <- PPU A11        /PPU A11 <- |02  23| <- PPU A11
   PRG A15 <- |03  22| <- PPU A12         PRG A15 <- |03  22| ?
   PRG A14 <- |04  21| <- CPU A13         PRG A14 <- |04  21| <- CPU A13
       VCC -- |05  20| <- CPU A14             VCC -- |05  20| <- CPU A14
   PRG /CE <- |06  19| <- /ROMSEL                  ? |06  19| <- /ROMSEL
   CHR A12 <- |07  18| <- RESET                    ? |07  18| <- RESET
   CHR A13 <- |08  17| -- GND           /RDWR8000 <- |08  17| -- GND
    CPU D7 -> |09  16| <- M2               CPU D7 -> |09  16| <- M2
    CPU D0 -> |10  15| <- CPU R/W          CPU D0 -> |10  15| <- CPU R/W
   CHR A16 <- |11  14| -> CHR A15       always 0? <- |11  14| -> always 0?
   CIR A10 <- |12  13| -> CHR A14         CIR A10 <- |12  13| -> /RDWRA000
              '------'                               '------'
               KS 203                                 KS 203
             in MMC1 mode                           in non-MMC1 mode


When in MMC1 mode, PRG/CHR/Mirroring/Mode registers, behaves same like on regular MMC1.
* One difference is that writing succesive bits can be done on every CPU cycle, even R/!W can remain low between writes. But after the last (fifth write), MMC1 need additional 2 cycles to apply changes. Those 2 cycles can be reads to anywhere $0000-$ffff or writes to $0000-$7fff). Making next 5 writes to $8000-$ffff without those 2 cycle gap will NOT work.
Image

When in non-MMC1 mode, it also has serial input register (D0) and also writes with D7=1 sets $8000.3-2 to ones, but meaning of bits inside registers differ:

Code:
[.XVMM] MODE REGISTER ($8000-$9fff)
  ||||
  ||++- mirroring: 00=1scA, 01=1scB, 10=V, 11=H
  ++--- PRG mode
           
[...BA] PRG BANK REGISTER ($e000-$ffff)
    ||
    ++- PRG bank bits

XV | $8000|$c000|
---+------+-----+
0* |    B0|   B1| NROM32
10 |    00|   BA| Inverted Semi-UNROM
11 |    BA|   11| Semi-UNROM

[....] $a000 - unused?

[....] $c000 - unused?


Pins 1 / 2:
They booth seems to output inverse of PPU-A11

Pins 8 / 13:
* Pin 8 goes low during read/write cycle at $8000-$9fff and pin13 $a000-$bfff, that is:
Code:
/RDWR8000 (pin8)  <= 0 when m2=1 and cpu_nromsel = 0 and cpu_a14=0 and cpu_a13=0 else 1
/RDWRA000 (pin13) <= 0 when m2=1 and cpu_nromsel = 0 and cpu_a14=0 and cpu_a13=1 else 1

* My only guess is that they were intendend to use as chip enable for external RAM (if they were for ROM or external register, r/w would be taken into account)
ks203 #2.logicdata

Pins 11 / 14: They output constantly 0

Pin 22: unused input?

Pin 7:
I have neither exact idea how it works nor purpose.
It goes low when CPU-A14 is high, CPU-W/W is low and M2 is high, but it does not seem to behave combinatorial.

Ping 6:
Similar like pin7 but CPU-A14 needs to be low
See waveforms below:

Image

I am wondering did they ever use this chip in that mode in any game? If so, what kind of ROM is that - multicart, FDS port?

Do we know any other game or mapper, beside MMC1, that has serial data input?
Re: Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243186)
I don't see a WRAM /CE pin in your description of "MMC1 mode". Is it possible that "MMC1 mode" is basically SLROM mode, while "non-MMC1 mode" is SNROM with WRAM mode?
Re: Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243189)
krzysiobal wrote:
Pin 7:
I have neither exact idea how it works nor purpose.
It goes low when CPU-A14 is high, CPU-W/W is low and M2 is high, but it does not seem to behave combinatorial.

Pin 6:
Similar like pin7 but CPU-A14 needs to be low
They're both almost combinatorial.

Code:
A14 R/W M2  pin 7
 0   0   0  almost always 0  (100ns propagation delay?? - e.g. at 7.3994ms)
 0   0   1  0
 0   1   0  1
 0   1   1  1
 1   0   0  often 1 - as though it latches A14 on a falling edge of M2, as well as caring about the current value of A14.
 1   0   1  usually 0 - other than power-on state, seems to be propagation delay again, e.g. at 0.3307ms. Consistent with above.
 1   1   0  1
 1   1   1  1


Code:
A14 R/W M2  pin 6
 0   0   0  1
 0   0   1  1
 0   1   0  1
 0   1   1  1
 1   0   0  often 1 - practically identical to pin 7 ( 6 exceptions out of 27359 )
 1   0   1  usually 0 - practically identical to pin 7 ( 5 exceptions out of 8508 )
 1   1   0  often 1 - similar "latching A14 on falling edge of M2" behavior. e.g. 0.659ms
 1   1   1  almost always 0 - only 1 during power-up.


Quote:
Do we know any other game or mapper, beside MMC1, that has serial data input?
Nestopia's source only uses the word "serial" in combination with MMC1, for whatever that's worth.
Re: Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243191)
The only other serial mapper I know of in a game console is in front of the Z80 in the Sega Genesis, which uses a 9-bit serial register to bankswitch 32K sections of 68000 memory.
Re: Kaiser chips KS204/KS203/KS202 + kaiser boards
by on (#243210)
Oh, now I realized that the description for PRG banking in non-MMC1 mode that I wrote is exactly how MMC1 works, just cut down to PRG-A15 and PRG-A14 (max 64 kB ROM), so that's nothing new :oops:

That would mean this mode can be used for MMC1 games with up to 64 kB PRG-ROM and CHR either as RAM or controlled in different way (because CHR regs are gone).

Quick look at bootgod database shows that there are no MMC1 games with 64 kB PRG-ROM and PRG-RAM :(

I though they repurposed those missing high PRG/CHRR bits into some cycle counter, but trying to inject lot of M2/PPU-A12 pulses did not change state of the output pins 11/14 which are still constantly held at 0 or the pin1/2 which always output inverse of PPU-A11.

After digging more about the `KS-7058: Game: ?, Mapper: 171`, I found it is Kaiser made Chinese game, called:
Tui Do Woo Ma Jeung (Ch) [!] - MMC1 with fixed mirroring, PRG=32 kB, CHR= 32kB. It probably uses this chip but in MMC1 mode, just ignoring mirroring, so that's not this case.
Image Image


Quote:
I don't see a WRAM /CE pin in your description of "MMC1 mode". Is it possible that "MMC1 mode" is basically SLROM mode...

There are not enough pins for WRAM /CE. If they wanted it, they would use just external AND gate or 4 diodes and ressitor.

Quote:
.. while "non-MMC1 mode" is SNROM with WRAM mode?

Non-MMC1 stil has no pins that would act as RAM chip enable for $6000-$7fff. Rather need to find a ROM that switches PRG bank like ordinary MMC1 but has RAM at $8000-$9fff.

Quote:
They're both almost combinatorial..

Good find! So this behaviour resembles the KS204 in VRC2 mode, but here it is latched on every write at $0000-$ffff, which is still useless.