I'm trying to re-implement the MMC1 chip in an FPGA and am having some trouble understanding a few things about it.
1. Why is the PRG A13 line connected to the MMC1 chip? I don't see any reason why it should need this line, as it only distinguishes between 8KB banks and MMC1 operates on banks of at least 16KB. What is it used for?
2. PRG_CE line also goes to MMC1, and I'm not sure why. I don't see any reason for this. As far as I can tell MMC1 takes PRG_CE in from the 2A03 and outputs another CE line that goes to the ROM chip, but I don't see any difference in the two signals. Is MMC1 just a passthrough for this signal, and if so, why not just route the line from the 2A03 to the ROM?
3. CHR A10 is an output of the 2C02 and is connected to both the MMC1 chip and the CHR ROM. To do mirroring the MMC1 chip has to force this line low in certain situations. How is this not a bus contention problem if both the 2C02 and the MMC1 are driving this pin?
Thanks for the help, I'll post my schematics and Verilog code as soon as I've tested it in a real cart.
1. Why is the PRG A13 line connected to the MMC1 chip? I don't see any reason why it should need this line, as it only distinguishes between 8KB banks and MMC1 operates on banks of at least 16KB. What is it used for?
2. PRG_CE line also goes to MMC1, and I'm not sure why. I don't see any reason for this. As far as I can tell MMC1 takes PRG_CE in from the 2A03 and outputs another CE line that goes to the ROM chip, but I don't see any difference in the two signals. Is MMC1 just a passthrough for this signal, and if so, why not just route the line from the 2A03 to the ROM?
3. CHR A10 is an output of the 2C02 and is connected to both the MMC1 chip and the CHR ROM. To do mirroring the MMC1 chip has to force this line low in certain situations. How is this not a bus contention problem if both the 2C02 and the MMC1 are driving this pin?
Thanks for the help, I'll post my schematics and Verilog code as soon as I've tested it in a real cart.