I am in a way of building KrzysioGenie - an utility cartridge which will offer features of Game Genie (modyfying ROM value - for example in order to cheat) and Action Replay (save/load game state into micro SD card).
When I first read about the idea how Gallob's Game Genie works, it looked amazingly simple & briliant to me.
I rev-ed its PCB:
Those resistor between gallob's data bus and cpu data bus are quite weird to me, but maybe gallob's data bus is not tristate and that's the reason.
However, the process of replacing memory value WHEN DATA COMPARISION IS TURNED ON is unclear to me. What is unclear is when Game Genie's chip detect that there is right moment to read CPU's data & address bus and if they match, turn off cartridge's PRG-ROM and put his own value on data bus?
*1. It can't do that on falling edge of ROMSEL because cartridge's PRG-ROM has not placed data on the bus yet
*2. It can't do that on rising edge of ROMSEL because even if it put his own value on data bus and disabled cartridge's PRG-ROM memory, it would take tens of ns for the memory to turn off, but CPU fetches data almost immediatelly after falling edge of M2 (and rising of ROMSEL) so it would fetch garbage,
*3. it can't do that asynchronously when ROMSEL is low because there data bus is unstable and it could detect transient state on data bus as a final data and start process of replacing it,
*4. it also can't do that after some fixed amount of time after falling edge of ROMSEL because there is no external timer components (R/C) nor faster crystal oscillator, but maybe they are inside gallob's chip?
Or maybe it does 2) and the aim of the resistor is to minimize current flow upon bus conflict (when memory hasn't fully turn off yet but game genie put its values on?)
When I first read about the idea how Gallob's Game Genie works, it looked amazingly simple & briliant to me.
I rev-ed its PCB:
Those resistor between gallob's data bus and cpu data bus are quite weird to me, but maybe gallob's data bus is not tristate and that's the reason.
However, the process of replacing memory value WHEN DATA COMPARISION IS TURNED ON is unclear to me. What is unclear is when Game Genie's chip detect that there is right moment to read CPU's data & address bus and if they match, turn off cartridge's PRG-ROM and put his own value on data bus?
*1. It can't do that on falling edge of ROMSEL because cartridge's PRG-ROM has not placed data on the bus yet
*2. It can't do that on rising edge of ROMSEL because even if it put his own value on data bus and disabled cartridge's PRG-ROM memory, it would take tens of ns for the memory to turn off, but CPU fetches data almost immediatelly after falling edge of M2 (and rising of ROMSEL) so it would fetch garbage,
*3. it can't do that asynchronously when ROMSEL is low because there data bus is unstable and it could detect transient state on data bus as a final data and start process of replacing it,
*4. it also can't do that after some fixed amount of time after falling edge of ROMSEL because there is no external timer components (R/C) nor faster crystal oscillator, but maybe they are inside gallob's chip?
Or maybe it does 2) and the aim of the resistor is to minimize current flow upon bus conflict (when memory hasn't fully turn off yet but game genie put its values on?)
