MMC1 double writes blocking - explicit register or CPU R/W ?

MMC1 double writes blocking - explicit register or CPU R/W ?
by on (#192125)
So it's a well doccumented fact that MMC1 ignores double writes, only the first write cycle of a multi-write cycle is acknownledge. With a raw 6502 processor only incrementing, decrementing and shifting instructions can do double writes outside of the stack page, and nothing can do triple or more writes in a row. However there is conflicting info about how it manages to have this "feature".

In this post dating back to 2012, infinitelives is very confident that the MMC1 has an explicit register who remembers if the last operation, and only allows the shift register to shift or be reseted if the last operation was a read. The range would be ignored - even a write on $0000-$7fff would prevent a consecutive write to $8000-$ffff to affect the shift registers - even though such a situation cannot happen with the CPU. He said he explicitely tested the MMC1, and that R/W cannot possibly be used as a clock.

On the wiki there is the following "evidence" :
#nesdev IRC chat, 2015/05/23. kevtris: "I think I figured out why the MMC1 ignores the second write. It seems to be because it uses R/W as a clock, and it stays low for 2 cycles, instead of pulsing so only the first is written."

This is in total contradictions with infinitelives' finding. Since the evidence is weak (just "this guy said that") I would be tempted to reject it as being fake, but I am still withing to understand the truth and cannot ignore any possibility.

Finally, even in the possibility that somehow Infinitelives was wrong and that R/W is actually used to clock the registers, I think the MMC1 wouldn't work at all if this was done, because the R/W line would be changing when Phi2 is low, and the adress/data lines could be unstable at that point. So we could end up having a MMC1 shift register randomly written to or reset due to the MMC1 behaving on incorrect data before the A13, A14, D0 and D7 lines are ready. This leads me to belive infinitelives is right and Kevtris is wrong, despite the fact his statement is more recent (2015).
Re: MMC1 double writes blocking - explicit register or CPU R
by on (#192140)
I had an idea to test my findings without my kazzo rig be relied upon.

Using SLROM test board, make a switch that disconnects M2 from the MMC1. Tie the M2 input to gnd to disable WRAM decoding. I expect games that don't test double writes will work, and bill and ted won't.

From my findings M2 is used for WRAM decoding, and blocking double writes alone. The shift register works without M2 as an input.
Re: MMC1 double writes blocking - explicit register or CPU R
by on (#192188)
Which version(s) of the MMC1 did you test it on ? Perhaps Kevtris tested another MMC1 ? Or perhaps he's just plain wrong ?

EDIT : I just looked at the 6502 datasheet to double check, and effectively, the data lines aren't supposed to be stable on a write cycle when R/W goes low, they're only stable on the rising edge of phi2, and the data lines are stable only at the falling edge of phi2. So an hypothetical MMC1 who would be clocked by the R/W line would probably be broken anyway since it'd use incorect adress and data line when R/W falls.
Re: MMC1 double writes blocking - explicit register or CPU R
by on (#192208)
It didn't sound like kevtris' random comment on irc was based on a bunch of testing. Sounds off the cuff, like he realized R/W doesn't toggle and "thinks" that might to do with what's going on. He specifically used the work "think" which is rather telling to me. Yes he's the god of NES REing but IMO he was just making a comment. Not reporting results of actual testing. I don't have much interest in proving kevtris wrong. My previous testing already proved what's going on enough for my own mind. Whether or not people want to believe my results or not doesn't affect me.

I gave a simple method of how anyone with a SLROM test board could prove my theory with separate findings if they cared enough.

Honesty I don't really care anymore.. I still have the board I used somewhere and can check its version. If there's actual testing going on where the chip version might matter I'll take the time to dig it up. Kevtris didn't make his comment about a specific mmc1 version anyway.
Re: MMC1 double writes blocking - explicit register or CPU R
by on (#192257)
OK so as usual the wiki was wrong and is referenced on a mere "thought" by kevtris. I'll edit this out and this whole thread can be disregarded since everything is already discussed in the thread I linked to in the original post.