Pirate Kid Dracula reverse engineering

              .--V--.
   /ROMSEL -> |1  20| -- +5V
    CPU A2 -> |2  19| -> CNT CLEAR
    CPU A3 -> |3  18| ?? nc
   CPU A14 -> |4  17| ?? nc
    CPU D0 -> |5  16| ?? nc
    CPU D1 -> |6  15| ?? nc
       R/W -> |7  14| -> /IRQ
VRC2 NTA10 -> |8  13| ?? nc
    CNT=86 -> |9  12| -> CIRAM A10
       Gnd -- |10 11| ?? nc
              '-----'

           .--V--.
     A0 -> |1  20| -- +5
     A1 -> |2  19| -> D5
     A2 -> |3  18| -> D4
     A3 -> |4  17| -> D3
     A4 -> |5  16| ?? A10
     A5 -> |6  15| -> D2
     A6 -> |7  14| -> D6
     A7 -> |8  13| -> D1
     A8 -> |9  12| -> D0
    Gnd -- |10 11| <- nc
           '-----'

Mask: $C00C
  $8000: no effect
  $8004: [.... ..Mm] - mirroring override
                 ||
                 |+--  0: 1-screen A mirroring, 1: 1-screen B mirroring
                 +---  0: Mirroring from VRC2, 1: Mirroring from m bit
         These two bits are stored in the PAL's outputs-
          M on pin 17
          m on pin 18
  $8008: Functionality not knowable from available dump
  $800C: Functionality not knowable from available dump
  $C000: no effect
  $C004: Acknowledge IRQ
  $C008: ?start IRQ counter?
  $C00C: Acknowledge and ?stop counter?

           .--V--.
     A0 -> |1  20| -- +5
     A1 -> |2  19| -> D7
     A2 -> |3  18| -> D6
     A3 -> |4  17| -> D5
     A4 -> |5  16| ?? D4
     A5 -> |6  15| -> D3
     A6 -> |7  14| -> D2
     A7 -> |8  13| -> D1
     A8 -> |9  12| -> D0
    Gnd -- |10 11| <- nc
           '-----'

========================
=  Mapper "18-72"      =
========================


Example Games:
--------------------------
Akumajou Special: Boku Dracula-kun (pirate version)


Notes:
--------------------------
This mapper is another pirate VRC2b, this time with IRQs and VRC4-style
mirroring.

A mapper number hasn't been assigned to this particular board yet.


Registers:
---------------------------
There are two sets of registers: the VRC2 registers, and the Extra registers.
Writes will affect both sets of registers!


VRC2 registers range, mask: $8000-$FFFF, $F003

$8000-$8003:  [...P PPPP]   Same as VRC2b (PRG select 0)
$9000-$9003:  [.... ...M]   VRC2 mirroring control (see extra registers)
                       |
                       +- 0: vertical (A10); 1: horizontal (A11)

$A000-$A003:  [...P PPPP]   Same as VRC2b (PRG select 1)
$B000-$E003:  [.... CCCC]   Same as VRC2b (CHR select)



Extra registers range, mask: $8000-$FFFF, $C00C

$8004:        [.... ..XX]   Extended mirroring control
                      ||
                      ++- Extended mirroring control
                           0x: Let VRC2 control mirroring
                           10: one-screen, lower bank (overrides VRC2)
                           11: one-screen, upper bank (overrides VRC2)

$C004:        [.... ....]   Acknowledge IRQ
$C008:        [.... ....]   Start IRQ counter
$C00C:        [.... ....]   Acknowledge IRQ and hold IRQ counter at 0


Mirroring behavior:
---------------------------
Games will write to $9004 to affect both the VRC2 mirroring register ($9000)
and the Extra mirroring register ($8004) at the same time. The result is like
VRC4 mirroring:

$9004 [.... ..MM]   Combined VRC2 and Extra mirroring control
              ||
              ++- VRC4 mirroring
                   00: Vertical
                   01: Horizontal
                   10: One-screen, lower bank
                   11: One-screen, upper bank

The VRC2 will remember the last setting written to it, even if the Extra
mirroring control is overriding it.


IRQ behavior:
---------------------------
The IRQ counter counts falling edges of PPU A13. The IRQ is asserted every time
the counter reaches 86. When the counter reaches 86, it's automatically reset
to 0. This results in one IRQ every two scanlines, as long as the counter is
running. Writing to Extra register $C004 or $C00C will acknowledge the IRQ.
Writing to Extra register $C00C will hold the counter at 0, and writing to
Extra register $C008 will allow the counter to resume.

Games will typically write to addresses like $F004/$F008/$F00C to control the
IRQ without affecting the VRC2's registers.

sorry

O6 <= D0 when CPU-!ROMSEL=0 and R/!W=0 and A14=0 and A3=0 and A2=1; --latch

O5 <= D1 when CPU-!ROMSEL=0 and R/!W=0 and A14=0 and A3=0 and A2=1; --latch

02 <= 0 when CPU-!ROMSEL=0 and R/!W=0 and A14=1 and A3=1 and A2=1 else --latch
      1 when CPU-!ROMSEL=0 and R/!W=0 and A14=1 and A3=1 and A2=0;

!IRQ! <= 1 when CPU-!ROMSEL=0 and R/!W=0 and A14=1 and A3=0 and A2=1 else  --latch
         1 when CPU-!ROMSEL=0 and R/!W=0 and A14=1 and A3=1 and A2=1 else
         0 when (CPU-!ROMSEL!=1 or R/!W=1) and IRQ_PEN = 1 else
       0 when CPU-!ROMSEL=0 and R/!W=0 and A14=0 and A3=1 and A2=1
    
CLR <= not O2 or IRQ_PEN

CIRAM <= 0 when O6=0 and O5=1  else
       1 when 06=1 and 05=1  else
       VRC-CIRAM
         
      a a a  dddd dddd
      1 3 2  7654 3210
      4
     -----------------
$8004 0 0 1 [.... ..mm] mm - mirroring (source of ciram) (0/1: VRC-CIRAM, 2:GND, 3: VCC)
$800c 0 1 1 [.... ....] writing any value forces interrupt to be triggered
$c004 1 0 1 [.... ....] writing any value acknowledges pending interrupt
$c008 1 1 0 [.... ....] writing any value resets counter from clear
$c00c 1 1 1 [.... ....] writing any value holds counter in clear & acknowledges pending interrupt

* counter is automatically cleared when interrupt becomes pending
* interrupt is triggered when IRQ_PEN=1 and (CPU-!ROMSEL! = 1 or R/!W=1)

#include "mapinc.h"

static int prg[2];
static int mirr;
static int chr[8];
static int last_pa13;
static int counter;

static int pal_mirr;
static int counter_canclock;

static SFORMAT StateRegs[] =
{
   { 0 }
};


//shifts bit from position `bit` into position `pos` of expression `exp`
#define shi(exp, bit, pos) \
   ((((exp) & (1 << (bit))) >> (bit)) << (pos))

static void M272Hook(uint32 A) {
   int pa13 = (A >> 13) & 1;
   if ((last_pa13 == 1) && (pa13 == 0)) {
      if (counter_canclock) {
         counter++;
         if (counter == 84) {
            counter = 0;
            X6502_IRQBegin(FCEU_IQEXT);
         }
      }
   }
   last_pa13 = pa13;
}

static int vrc_addr_mix(int A) {
   //this game wires A0 to VRC_A0 and A1 to VRC_A1
   return (A & 0xf000) | shi(A, 0, 0) | shi(A, 1, 1);
}

static void Sync(void) {
   setprg8(0x8000, prg[0]);
   setprg8(0xa000, prg[1]);
   setprg16(0xc000, -1);   
   for (int i = 0; i < 8; ++i) {
      setchr1(0x400 * i, chr[i]);
   }
   
   switch (pal_mirr) {
   case 2: setmirror(MI_0); break;
   case 3: setmirror(MI_1); break;
   default:
      switch (mirr) {
      case 0: setmirror(MI_V); break;
      case 1: setmirror(MI_H); break;
      }
   }
}

static DECLFW(M272Write) {
   //writes to VRC chip
   switch (vrc_addr_mix(A)) {
   case 0x8000:
   case 0x8001:
   case 0x8002:
   case 0x8003:
      prg[0] = V;
      break;
   case 0xA000:
   case 0xA001:
   case 0xA002:
   case 0xA003:
      prg[1] = V;
      break;
   case 0x9000:
   case 0x9001:
   case 0x9002:
   case 0x9003:
      mirr = V & 1;
      break;
   case 0xb000: chr[0] = (chr[0] & 0xF0) | (V & 0xF); break;
   case 0xb001: chr[0] = (chr[0] & 0xF) | ((V & 0xF) << 4); break;
   case 0xb002: chr[1] = (chr[1] & 0xF0) | (V & 0xF); break;
   case 0xb003: chr[1] = (chr[1] & 0xF) | ((V & 0xF) << 4); break;
   case 0xc000: chr[2] = (chr[2] & 0xF0) | (V & 0xF); break;
   case 0xc001: chr[2] = (chr[2] & 0xF) | ((V & 0xF) << 4); break;
   case 0xc002: chr[3] = (chr[3] & 0xF0) | (V & 0xF); break;
   case 0xc003: chr[3] = (chr[3] & 0xF) | ((V & 0xF) << 4); break;
   case 0xd000: chr[4] = (chr[4] & 0xF0) | (V & 0xF); break;
   case 0xd001: chr[4] = (chr[4] & 0xF) | ((V & 0xF) << 4); break;
   case 0xd002: chr[5] = (chr[5] & 0xF0) | (V & 0xF); break;
   case 0xd003: chr[5] = (chr[5] & 0xF) | ((V & 0xF) << 4); break;
   case 0xe000: chr[6] = (chr[6] & 0xF0) | (V & 0xF); break;
   case 0xe001: chr[6] = (chr[6] & 0xF) | ((V & 0xF) << 4); break;
   case 0xe002: chr[7] = (chr[7] & 0xF0) | (V & 0xF); break;
   case 0xe003: chr[7] = (chr[7] & 0xF) | ((V & 0xF) << 4); break;
      
   default:
      break;
   }

   //writes to PAL chip
   switch (A & 0xC00C) {
   case 0x8004: pal_mirr = V & 3; break;
   case 0x800c: X6502_IRQBegin(FCEU_IQEXT); break;
   case 0xc004: X6502_IRQEnd(FCEU_IQEXT); break;
   case 0xc008: counter_canclock = 1; break;
   case 0xc00c: counter_canclock = 0; counter = 0; X6502_IRQEnd(FCEU_IQEXT); break;
   }

   Sync();
}

static void M272Power(void) {
   SetWriteHandler(0x8000, 0xFFFF, M272Write);
   SetReadHandler(0x8000, 0xFFFF, CartBR);
   Sync();
   
   last_pa13 = 0;
   counter = 0;
}

static void M272Reset(void) {
   last_pa13 = 0;
   counter = 0;
   Sync();
}

void Mapper272_Init(CartInfo *info) {
   info->Power = M272Power;
   info->Reset = M272Reset;
   PPU_hook = M272Hook;

   AddExState(&StateRegs, ~0, 0, 0);
}