FDS DRAM controller

FDS DRAM controller
by on (#180662)
Does anyone have an FDS and an oscilloscope or logic analyzer? I'm curious about several completely unimportant aspects of its DRAM controller.

Things like:
/RAS-only refresh? or /CAS-before-/RAS refresh? or Hidden refresh? (or NO refresh??)
How do CPU A0-A14 map through the multiplexers?
What selects between the two /CAS lines?
Re: FDS DRAM controller
by on (#180664)
I have both (FDS and access to a scope, no logic analyser). I'm not familiar with how to wire/hook up what you want to be tested, however, so I'm probably not a good candidate. Maybe Dead_Body?
Re: FDS DRAM controller
by on (#180670)
Given 'scope probes on /RAS and /CAS0:

/RAS-only refresh:
Code:
/RAS ¯¯¯___¯¯¯
/CAS ¯¯¯¯¯¯¯¯¯
/CAS-before-/RAS refresh:
Code:
/RAS ¯¯¯¯¯¯___¯¯¯
/CAS ¯¯¯______¯¯¯
Hidden refresh:
Code:
/RAS ¯¯¯______¯¯¯___¯¯¯
/CAS ¯¯¯¯¯¯_________¯¯¯
A normal read/write cycle:
Code:
/RAS ¯¯¯______¯¯¯
/CAS ¯¯¯¯¯¯___¯¯¯

The other questions require active hunting, unfortunately. I assume one of the CPU address lines directly controls which of the two /CAS lines is asserted, (i.e. /CAS0 would stay high when Axx was high, for some unknown xx)