Is there a good and easy way to delay prg /ce

As we know when we use PRG /CE and M2 to decode $6000-$7FFF, but they are not change at the same time. PRG /CE is the logical NAND of M2 and PRG A15. This is accomplished by sending M2 and PRG A15 into a 74LS139 two-to-four line decoder on the NES main board. This introduces a small delay of up to 33 ns between the time M2 rises and the time PRG /CE rises.
If this delay is too long it can cause unintentional writes to PRG RAM when writing to mapper registers $E000-$FFFF.


So in a cpld mappers, how to do this:(how to delay 33ns)

I think Crisis Force uses a resistor, a diode, and a capacitor on the WRAM /CE output to delay falls (start of a write cycle) but not rises (end of a write cycle). It's like half of a Schmitt trigger, and there's an article about synthesizing one in a CPLD. It might involve making your CPLD output 1 (disable) most of the time but high-Z when a WRAM write is desired, so that a resistor and capacitor pull the line down to 0. Or I might be talking out my behind.

I want to try to "uses a resistor, a diode, and a capacitor" way,but I don't have this cart, so I don't know how to connector and the value of the resistor and capacitor.

Is this OK

Your guesswork/analysis is correct: yes, it's a 1kΩ resistor, yes it's a 941/4148 class signal diode, yes it's an 82pF capacitor, and yes the other side of the capacitor is to ground.

You'll note that 1kΩ·82pF = 82ns, or noticeably more than the 15-30ns propagation delay, but substantially less than the 350ns M2-high duration.

This will do the job:

Is it means this way is better than " Crisis Force" way?
and can completely solve the problem "PRG /CE delay"

This way is almost identical to the "Crisis Force way".

The only practical difference is whether you want to modify M2 for subsequent logic (krzysiobal's) or modify the emitted signals before it drives the RAM (Crisis Force).

You only need to worry about glitches if, for some reason, you have to distinguish between writes to address X and (X XOR $8000), as on mappers that put RAM at $6000-$7FFF and control registers at $E000-$FFFF.

Reads from these two different addresses don't matter, because no cart hardware changes things in response to the read strobe. (If it did, it'd pose problems with the DPCM glitch)

Thank you.
BTW. Is there a best value for this circuit,68ns ?(1K * 68pf) or others?

Let's say you want to feed the output of this `delayed` M2 into CPLD or FPGA. You look into this chip datasheet and you find out that


"0" logic level is 0-0.8 V
"1" logic level is 2.0V - VCC + 0.5V
The 0.8V-2.0V zone is forbidden, that is you increase smoothly the input voltage from 0 to 5V, the input logic level may switch from "0" to "1" at any voltage between 0.8 - 2.0V. So we must take into account the worst case, which is 0.8V.
Now, let'say the M2 logic level was "0" and has switched to "1" in time t0=0. The voltage on capacitor (which is FPGA m2 input pin) is increasing exponentially with constant RC


that is the voltage is given by formula:


We want to ensure the voltage will rise to V1=0.8V not faster than at t1=33ns.
Lets calculate correct C for that.


Now, lets assume we have R=1k.


That is 40pF is enough. If we put larger capacitor, the time will be longer that 33 ns.

I see.
Thank you again.