lidnariq wrote:
C1 changes the frequency [of the time base of the ramp-compare DAC in the Arkanoid controller] as it charges. It should stabilize pretty rapidly, and should only affect conversions in the first several seconds.
That may be part of why
Arkanoid has about 12 seconds of unskippable music before the player gets control: an 8-second jingle on the title screen after pressing Start, and then a 4-second jingle before each level. I'd like to be able to add a screen to
Vaus Test to characterize the power-on behavior of this in order to determine the implications for controlling the Action 53 menu. But the PowerPak inserts its own interstitial screens (PowerPak title, Game Genie code list, and loading the game), which means the cap is already charged by the time my code gets control.
lidnariq wrote:
When the monostable timer completes:
* One quarter of the NAND gate generates a very short pulse that loads the current contents of the 4040 counter into the shift register
I previously determined that the monostable timer completes within 7 to 8 ms. This allows reading once per frame, or twice if very careful, but it rules out the sort of rereading typical of DPCM safety routines. Instead, I recommend detecting bit deletions as an out-of-bounds second difference in the angular displacement.
lidnariq wrote:
Before the conversion finishes, this provides a direct measurement of the higher frequency clock, toggling every time that clock source finishes a cycle
It should be possible to measure this from the NES. Assuming that it takes 512 clocks in 7 ms, that's 315/176 MHz * 7000 us/read * 1 read/512 clocks = 24 CPU cycles per DAC time base cycle. An unrolled read loop at 8 CPU cycles per read should be able to sample the DAC time base at 3 reads per DAC time base cycle. One could try adding a module like this to Vaus Test.