Reviewing the MMC1 SxROM upper CHR lines on the wiki I found an interesting point yesterday that supposedly SOROM uses the second highest CHR address bit (CHR-ROM A15) to select the 8KB WRAM bank.
I had always thought it was the highest bit (A16). Pretty sure I got that idea in my head from one of two sources, Kevtris which claims the highest bit, although it's confusing how he shifts things in 4KB mode.. Or I learnt it from disch's docs. My copy of disch's docs agreed A16, but just now I downloaded the currently release from romhacking. The current copy of disch doc's actually agree with the wiki (A15).
Based on that modification to disch's docs and current wiki info I'm guessing it was determined sources claiming A16 were wrong, and it's actually A15.
Don't have an SOROM cart to verify for myself, but probably going to pick one up when I can gotta catch em all.. Trying to glean info from bootgod's database doesn't give much as all US carts are front side of PCB pics only with no traces leaving the top layer from those pins. The JP version does have bottom pics. While inconclusive based on photo alone, there is a trace leaving the A15 pin which goes to a via under the MMC1 chip. Assuming that via is useful and ends up controlling the WRAM bank that would agree with the wiki and current version of disch docs.
Tried some Koei games on my boards and not sure I even found a place to save, was unable to find a loadable game reguardless of what bit I used.
Tried Holy Diver Batman, and got interesting results..
A16 used for WRAM bank select: Seen as good SNROM (8KB RAM OK)
A15 used for WRAM bank select: Craziness S*ROM 24KB RAM PROBLEM
A14 used for WRAM bank select: S*ROM 16KB RAM PROBLEM
A15&A14 used for WRAM bank select: Seen as good SXROM (32KB RAM OK)
Now perhaps the PRG RAM PROBLEM is stemming from how I only implemented chr bank 0 in my logic simplifing out chr bank 1 since one should have both match, or use 8KB CHR bank mode. But how Holy Diver Batman sees 24KB of WRAM when there clearly is none sounds like a bug, might be cause of the curve ball I threw with only using chr bank 0 though I suppose... I should implement both banks and see what Holy Diver Batman says.
So anyway, any background discussion burried on the net that occurred on this to change disch's docs? Or has/can someone verify this with a multimeter and an original SOROM board before mine arrives?
EDIT: on closer read, my old disch docs shifted things around like Kevtris did in 4KB mode, so perhaps he just copied info from Kevtris which was the source of the suspected bad info?
I had always thought it was the highest bit (A16). Pretty sure I got that idea in my head from one of two sources, Kevtris which claims the highest bit, although it's confusing how he shifts things in 4KB mode.. Or I learnt it from disch's docs. My copy of disch's docs agreed A16, but just now I downloaded the currently release from romhacking. The current copy of disch doc's actually agree with the wiki (A15).
Based on that modification to disch's docs and current wiki info I'm guessing it was determined sources claiming A16 were wrong, and it's actually A15.
Don't have an SOROM cart to verify for myself, but probably going to pick one up when I can gotta catch em all.. Trying to glean info from bootgod's database doesn't give much as all US carts are front side of PCB pics only with no traces leaving the top layer from those pins. The JP version does have bottom pics. While inconclusive based on photo alone, there is a trace leaving the A15 pin which goes to a via under the MMC1 chip. Assuming that via is useful and ends up controlling the WRAM bank that would agree with the wiki and current version of disch docs.
Tried some Koei games on my boards and not sure I even found a place to save, was unable to find a loadable game reguardless of what bit I used.
Tried Holy Diver Batman, and got interesting results..
A16 used for WRAM bank select: Seen as good SNROM (8KB RAM OK)
A15 used for WRAM bank select: Craziness S*ROM 24KB RAM PROBLEM
A14 used for WRAM bank select: S*ROM 16KB RAM PROBLEM
A15&A14 used for WRAM bank select: Seen as good SXROM (32KB RAM OK)
Now perhaps the PRG RAM PROBLEM is stemming from how I only implemented chr bank 0 in my logic simplifing out chr bank 1 since one should have both match, or use 8KB CHR bank mode. But how Holy Diver Batman sees 24KB of WRAM when there clearly is none sounds like a bug, might be cause of the curve ball I threw with only using chr bank 0 though I suppose... I should implement both banks and see what Holy Diver Batman says.
So anyway, any background discussion burried on the net that occurred on this to change disch's docs? Or has/can someone verify this with a multimeter and an original SOROM board before mine arrives?
EDIT: on closer read, my old disch docs shifted things around like Kevtris did in 4KB mode, so perhaps he just copied info from Kevtris which was the source of the suspected bad info?