Specifically either FDS audio, or an extra APU emulation layer (with no DMC) for Sound Effects, But no-one has made such a mapper yet, except OneBus (VRT Technologies), ZZO had the idea for the latter, and seems good, but FDS takes less space to write for.
Should someone create the next mapper, Think about the capabilities they are missing out on.
BTW: I would try to make a mapper, but all I have is a PowerPak, and there's no open-source mappers for it!
There are a few source-available mappers mentioned here:
viewtopic.php?t=7992If I were to design a new mapper, I'd personally start with something closer to FME7 or VRC6 than MMC3.
One thing MMC3 does semi-right is a scanline counter. It's fiddly to get multiple splits on the FME-7 for at least two reasons. First, because of how the banking and IRQ are overlapped on the same set of registers, anything writing to $8000 to change banks has to write the last $8000 value to memory too so that the IRQ handler can restore the value after setting a second split point in case the IRQ happens between the write to $8000 and the following write to $A000. You end up having to make $8000 more or less constant, reserve $C000 for DPCM, and have the IRQ always restore the register index to $A000, which brings you back to the same scheme as MMC3. Second, the CPU cycle counter starts counting when counting is reenabled. But reenabling counting happens inside the IRQ handler, and there can be up to a 7 cycle delay difference depending on what instruction happens to be executing in the main thread at any given time.
Another use for MMC3-with-sound is for music hacks of existing MMC3 games.
Regarding multiple split points with mappers equipped with CPU cycle based counters: it would be intelligent if instead of directly writing to the counter value, it would add the value you write to the counter registers (well, for a down-counting counter; for an up-counting one it would substract instead) so the IRQ timing would be insensitive to when you do your writes, assuming you do them not too late. Of course, the problem would be, how to set the counter to a known value? Either two more regs to allow direct write to the counter, or even simpler, a way to clear the counter, so the next add will have a predictable result.