As a side project to dumping the weird cart, I have been thinking in creating a simple bidirectional PC-NES interface that would let me peek and poke values from CPU memory space to, for example, see how does the mapper works.
I know that there's already something that would let me do this, a CopyNES, but that requires modifying a NES and its case, and it doesn't work as-is of a Famicom or a Famiclone.
Therefore a simple bitbanged protocol using the lines available on a NES controller port would be better. One would plug in a cartridge containing a bootloader that would load into RAM, and then you can swap the cartridge with the one you want to dump.
I would like also to keep the hardware to a minium, using as few parts as posible. My initial idea was, using a single 7474 and a 7400, build a two bit serial FIFO, whose clock would be NES controller CLK anded with the inversion of the last bit from the FIFO, and whose input data would be OUT0.
The NES will wait until the PC sets the second (last) latch from the 7474 to one, and keeps polling the read line until this goes low. The bits in the FIFO would not shift as the last bit is one.
When the PC wants to starts a transfer, it would set first latch to the bit it wants to send, and then it clears the second (last) latch. The NES while polling this register, will detect that it now reads as zero, and the next read would be pushed on the bit buffer.
To reply, the NES will wait until the FIFO is clear, and will then send a 1, and then the bit it wants to transfer. Therefore, if the FIFO is "10", the bit is a 0, and if it is "11", then the bit is a 1. As upper bit is 1, the NES can read the FIFO last bit without rotating the bits on the buffer. The PC will read this, and then it will clear the buffer, and wait for the next bit.
I have no CAD software right now, so I can't provide a schematic.
Another approach I though about was bitbanging SPI through the controller port, because there are enough signals to communicate with a SPI device, which could be a SRAM the PC could fetch at any time. However, SPI buses aren't multimaster, so we would have to add "busy" control signal, but the NES only has a single input.
I know that there's already something that would let me do this, a CopyNES, but that requires modifying a NES and its case, and it doesn't work as-is of a Famicom or a Famiclone.
Therefore a simple bitbanged protocol using the lines available on a NES controller port would be better. One would plug in a cartridge containing a bootloader that would load into RAM, and then you can swap the cartridge with the one you want to dump.
I would like also to keep the hardware to a minium, using as few parts as posible. My initial idea was, using a single 7474 and a 7400, build a two bit serial FIFO, whose clock would be NES controller CLK anded with the inversion of the last bit from the FIFO, and whose input data would be OUT0.
The NES will wait until the PC sets the second (last) latch from the 7474 to one, and keeps polling the read line until this goes low. The bits in the FIFO would not shift as the last bit is one.
When the PC wants to starts a transfer, it would set first latch to the bit it wants to send, and then it clears the second (last) latch. The NES while polling this register, will detect that it now reads as zero, and the next read would be pushed on the bit buffer.
To reply, the NES will wait until the FIFO is clear, and will then send a 1, and then the bit it wants to transfer. Therefore, if the FIFO is "10", the bit is a 0, and if it is "11", then the bit is a 1. As upper bit is 1, the NES can read the FIFO last bit without rotating the bits on the buffer. The PC will read this, and then it will clear the buffer, and wait for the next bit.
I have no CAD software right now, so I can't provide a schematic.
Another approach I though about was bitbanging SPI through the controller port, because there are enough signals to communicate with a SPI device, which could be a SRAM the PC could fetch at any time. However, SPI buses aren't multimaster, so we would have to add "busy" control signal, but the NES only has a single input.