NSF header question

Hi guys and gals
I need to confirm a question regarding the NSF header and banking control. I think I understand

When he mentions " loaded into RAM" he is referencing his hardware or a emulator NSF Player, right?
So If I had song data contiguous in say a flash device starting at $00. Loading $00 at reg $5FF8 would map a 4K block to the 2A03 address $8000 and loading $5FF9 with $01 would map the next 4k block to $9000.
Right ?
Yogi

There are two different cases:

1. Not bankswitched.
- You have a 40k block of RAM mapped to $6000.
- Copy the data from the NSF to the LOAD address in this block.
- Write protect $8000 to $FFFF, or if FDS expansion is used write protect only $E000-$FFFF.

2. Bankswitched.
- You have a 1MB block of RAM that is banked by the registers starting at $5FF8.
- Copy the data from the NSF to your RAM starting at an offset of LOAD & $0FFF.
- The bankswitch registers select a 4k bank from your RAM.
- The initial bank list should be applied before calling INIT.
- FDS NSFs can bank $6000, see the special rules for this.

For most NSFs, the RAM at $6000 can be omitted, and you could do with simply 32k of RAM at $8000, but some NSFs do need it.


Also, I highly advise reading the definition of the format on the wiki instead of the TXT file kevtris wrote 14 years ago. I'd like to think we've made things a little clearer by now:
http://wiki.nesdev.com/w/index.php/NSF

OK


Thanks, but the part that is confusing is the example

This implies that each reg is weighted by 4K. So reg $5ff8 has an offset of 0 + the load address + (header $70 byte x 4K). And $5ff9 would be 4K + Load address+ (header $71 byte x 4K). And writing $05 to the 8 regs creates a 32K ROM at $8000.
Thanks,
Yogi

When bankswitching is used, the high nibble of the LOAD address is to be ignored. Another way of thinking about it is that LOAD is just bytes of padding at the start of the ROM image you are building from the NSF file.

Yes, the number written to a bankswitch register specifies a 4k offset from the beginning of the ROM image you've created. In the hardware, the bits 12-14 of the CPU memory address will in your mapper look up the number stored in the register, and the resulting 8-bits become address lines 12-19 of your 1MB RAM chip.

Thank you that clears things up for me somewhat.
With the wiki example again $070: 05 05 05 05 05 05 05 05

Would this imply that 'bank 5' is >24K? or are all the 6502 PRG banks pointing to the same 4K block?

Anyways, thanks again
Yogi

All of them are pointing at the same 4k block.

OHHH.Now it makes sense!
Yogi