I know this is an odd request for Nesdev, but can someone help me with VHDL for a clock divider? I'm using a 50MHz clock and trying to get it down to 29Mhz. I can't seem to get it to work.
This is how I have it now (based off of a template I found online):
Any idea as to what is wrong here?
This is how I have it now (based off of a template I found online):
Code:
entity clock is
port ( CLKin: in std_logic;
reset: in std_logic;
CLKout: out std_logic);
end clock;
architecture arch of clock is
signal counter: integer:=0;
signal temp : std_logic := '1';
begin
process(CLKin,counter,reset)
begin
if(reset='0') then counter<=0; temp<='1';
elsif(CLKin'event and CLKin='1') then counter <=counter+1;
if (counter = 29000000) then temp <= NOT temp; counter<=0;
end if;
end if;
CLKout <= temp;
end process;
end arch;
port ( CLKin: in std_logic;
reset: in std_logic;
CLKout: out std_logic);
end clock;
architecture arch of clock is
signal counter: integer:=0;
signal temp : std_logic := '1';
begin
process(CLKin,counter,reset)
begin
if(reset='0') then counter<=0; temp<='1';
elsif(CLKin'event and CLKin='1') then counter <=counter+1;
if (counter = 29000000) then temp <= NOT temp; counter<=0;
end if;
end if;
CLKout <= temp;
end process;
end arch;
Any idea as to what is wrong here?