Hello, I've got tired of AVR microcontrollers for game projects (other than video rendering only, maybe) so I'm thinking of using a Z80 processor.
The Z80 processor must have address decoders, latches and AND gates in order to select the correct chips to communicate with.
I was thinking if all of the address/data bus is wired to an FPGA chip which is configurable to set the correct memory map.
By thinking of that, I've also realized that it would be awesome if the Z80 processor could have a virtualized memory by having different memory maps for different processes.
Here's my idea:
First, when you turn on or reset the console, both Z80 and FPGA start up at zero everything. The FPGA addresses only the chip with Chip Select 0 and that's the Flash ROM with the initialization program located where the interrupt vectors are. The processor finds its interrupt vector and jumps to the program start location. From there, it writes at address 0xFFFF the byte that determines the 256-byte page where the FPGA will map its control registers. In this case, 0xFF. From there, the processor writes to the FPGA registers at addresses from 0xFF00 to 0xFFFF the memory map which contains the address regions, address maps specific for when reading and writing. It writes the kernel-mode memory map and user-mode memory map. It then has a little counter that loops for multitasking. Then, the FPGA starts in kernel-mode. That gives Z80 the access to all chips and registers. Then, it runs a process which can be a cartridge or another Flash memory or another Flash memory region. Then, in that process, the address map is different because of the user-mode which prevents the processor from writing to unwanted memory regions. Even the FPGA registers are different for the user-mode because the kernel-mode decides which registers can the user-mode process access. When the counter reaches every 1ms, it calls the processor's Non-Maskable Interrupt and at that exact moment, the address map changes to kernel-mode and the processor jumps to the NMI interrupt vector and thereby to the kernel's code. From there, context switch is performed and some kernel-based stuff like writing the next process's context which is the stack and the user-mode address map. It goes on and on like that. Now, I gotta think of how the processes are added and removed. I think that there will be a RAM region for user-mode processes to write kernel-call information to and then the code should write to the kernel-call registers. That way the user-mode processes will be able to make new processes, which is of course if a particular one has permission to do so. The kernel code writes to the FPGA the user-mode information to prevent the user-mode processes from running spam processes or something nasty.
What do you think about this idea? Does this implementation already exist? What kind of a DIP packaged FPGA and Z80 should I get that run on 3.3v and at least at 16MHz synchronously? I want it to be DIP packaged to be more retro. I could easily get the SMD chips and their breakout boards if it's impossible to get the DIP ones, but if you know for the DIP ones, please tell me.
The Z80 processor must have address decoders, latches and AND gates in order to select the correct chips to communicate with.
I was thinking if all of the address/data bus is wired to an FPGA chip which is configurable to set the correct memory map.
By thinking of that, I've also realized that it would be awesome if the Z80 processor could have a virtualized memory by having different memory maps for different processes.
Here's my idea:
First, when you turn on or reset the console, both Z80 and FPGA start up at zero everything. The FPGA addresses only the chip with Chip Select 0 and that's the Flash ROM with the initialization program located where the interrupt vectors are. The processor finds its interrupt vector and jumps to the program start location. From there, it writes at address 0xFFFF the byte that determines the 256-byte page where the FPGA will map its control registers. In this case, 0xFF. From there, the processor writes to the FPGA registers at addresses from 0xFF00 to 0xFFFF the memory map which contains the address regions, address maps specific for when reading and writing. It writes the kernel-mode memory map and user-mode memory map. It then has a little counter that loops for multitasking. Then, the FPGA starts in kernel-mode. That gives Z80 the access to all chips and registers. Then, it runs a process which can be a cartridge or another Flash memory or another Flash memory region. Then, in that process, the address map is different because of the user-mode which prevents the processor from writing to unwanted memory regions. Even the FPGA registers are different for the user-mode because the kernel-mode decides which registers can the user-mode process access. When the counter reaches every 1ms, it calls the processor's Non-Maskable Interrupt and at that exact moment, the address map changes to kernel-mode and the processor jumps to the NMI interrupt vector and thereby to the kernel's code. From there, context switch is performed and some kernel-based stuff like writing the next process's context which is the stack and the user-mode address map. It goes on and on like that. Now, I gotta think of how the processes are added and removed. I think that there will be a RAM region for user-mode processes to write kernel-call information to and then the code should write to the kernel-call registers. That way the user-mode processes will be able to make new processes, which is of course if a particular one has permission to do so. The kernel code writes to the FPGA the user-mode information to prevent the user-mode processes from running spam processes or something nasty.
What do you think about this idea? Does this implementation already exist? What kind of a DIP packaged FPGA and Z80 should I get that run on 3.3v and at least at 16MHz synchronously? I want it to be DIP packaged to be more retro. I could easily get the SMD chips and their breakout boards if it's impossible to get the DIP ones, but if you know for the DIP ones, please tell me.