I was trying to test audio on my Esper Dream 2 cartridge via hotswap and I couldn't get any expansion sound to work properly. Things were mostly silent; toggling channel enable on the squares caused a mild pop, and volume output with the duty ignore mode on seemed to work. The saw was completely silent.
After some debugging of Esper Dream 2 and Akumajou Densetsu in FCEUX, I noticed these games both write $00 to $9003 on init. After trying this in my hotswap program, audio worked exactly as expected.
Does anyone know anything else about this? Is it some sort of "expansion sound enable" register? Any other details? Maybe it halts the clocking of the oscillators?
I notice PPMCK writes 0 to this address on init, with a comment that says "Sound initialize?"
Since you have the hardware, would you be willing to test what other written values do? It's possible only one of the bits actually enable it, or that the write itself enables things.
After testing the bits individually, this seems to happen for both square and saw channels:
%00000000 normal
%00000001 halted oscillator (if halted high, signal remains high until resumed)
%00000010 high frequency
%00000100 very high frequency
%00001000 normal
%00010000 normal
%00100000 normal
%01000000 normal
%10000000 normal
So, I am guessing it's a clock divider control. So far it seems like:
D0 disables the divider if on
D1 divides 16x faster
D2 divides faster again
Hard to tell the frequency ratios from my first test; I don't have any tools for dealing with RF. I'll try to set the oscillators to lower frequencies for the next test.
After doing a second test with the whole range of values, it looks very much like:
D0: halts divider if set
D1: 16x frequency if set
D2: 256x frequency if set
D3-D7: unused
If D2 is set, D1 does not matter. Frequency is still 256x.
If D0 is set, D1/D2 do not matter. Oscillators are halted.
I'll add this information to the wiki.
That's weird. I'm not certain where the extra octaves could come from short of increasing the increment step to the dividers. Unfortunately, without an oscilloscope or logic analyzer (the 6 audio out pins go into a DAC, so the pre-DAC voltages are full-scale) I have no idea how to test it.
Could just be a shift of the frequency registers. For audio purposes the internal details don't really matter i guess. Especially since it's not really a useful feature.
Shifting the frequency registers might be useful on certain non-NES platforms that clock the sound chip only once per scanline.
After taking some more accurate measurements, it does seem like it's a shift; the resulting frequency is consistently slightly high of 16x/256x, suggesting a round down / truncation.
Randomly guessing: The counter could be implemented using a set of 4-bit counters, and these bits select which of the 3 4-bit counters gets the clock pulses from M2. If so, I'd expect that values that were truncated were all be quantized together, so periods of e.g. 255 and 241 would sound the same with the ×16 mode.
I've now measured them accurately enough, and verified that 16x mode ignores the low 4 bits in the period register, 256x mode ignores the low 8 bits.
Other notes of interest:
The pulse and saw wave phases can be reset by clearing the enable bit in $X002.
The pulse duty cycles begin with 0 and end at the volume setting. The duty width in $9000/$A000 corresponds to the width of the high period at the end of the cycle.
The resulting waveform when compared to equivalent settings on the 2A03 pulse channels will appear inverted.
rainwarrior wrote:
I've now measured them accurately enough, and verified that 16x mode ignores the low 4 bits in the period register, 256x mode ignores the low 8 bits.
You mean... for emulation purposes, freq >> 4 or freq >> 8, right?
Exactly that, yes.
Edit: to clarify, if the 12-bit period register is currently 0xABC, with D1 enabled, you should treat it as 0x0AB, and with D2 enabled you should treat it as 0x00A.
The frequency is not exactly 16x or 256x, since the number is being truncated, and also the actual output frequency formula has a +1 on the value in the 12-bit register which still applies even when truncated to 8 or 4 bits.
Enabling these bits does not alter the actual contents of the period register; restoring them to 0 will restore the original pitch. You can still modify them and they will hold their value whether or not they're all currently being used in the clock divider.