I was just dorking around more with Visual2A03 [my favorite topic lately], trying to completely understand the DMC DMA and its impact. I recognize that there's lots of talk about how a DMC DMA can cause an extra controller read. I happened to be just randomly trying to find out how many cycles RDY is held in different situations, and created the following program.
The output of this surprised me a bit, and got me thinking...DMC DMA could maybe cause skipped frames.
Here's the relevant portion of the log:
At cycle 38, read $2002 has gone on the bus and RDY is asserted. Then in cycle 40 the DMC DMA happens. Then cycle 41, read $2002 goes back on the bus.
The pattern above is identical regardless of the address being read, obviously...so it makes me think that the above pattern is representative of the $4016/$4017 extra reads.
The output of this surprised me a bit, and got me thinking...DMC DMA could maybe cause skipped frames.
Here's the relevant portion of the log:
Code:
cycle ab db rw Fetch pc a x y s p c_rdy
34 4015 40 0 0015 10 c0 00 bd nv‑Bdizc 1
34 4015 10 0 0015 10 c0 00 bd nv‑Bdizc 1
35 0015 ad 1 LDA Abs 0015 10 c0 00 bd nv‑Bdizc 1
35 0015 ad 1 LDA Abs 0015 10 c0 00 bd nv‑Bdizc 1
36 0016 02 1 0016 10 c0 00 bd nv‑Bdizc 1
36 0016 02 1 0016 10 c0 00 bd nv‑Bdizc 1
37 0017 20 1 0017 10 c0 00 bd nv‑Bdizc 1
37 0017 20 1 0017 10 c0 00 bd nv‑Bdizc 1
38 2002 00 1 0018 10 c0 00 bd nv‑Bdizc 1
38 2002 00 1 0018 10 c0 00 bd nv‑Bdizc 0
39 2002 00 1 0018 00 c0 00 bd nv‑BdiZc 0
39 2002 00 1 0018 00 c0 00 bd nv‑BdiZc 0
40 c000 e0 1 0018 00 c0 00 bd nv‑BdiZc 0
40 c000 e0 1 0018 00 c0 00 bd nv‑BdiZc 0
41 2002 00 1 0018 e0 c0 00 bd Nv‑Bdizc 1
41 2002 00 1 0018 e0 c0 00 bd Nv‑Bdizc 1
42 0018 10 1 BPL 0018 00 c0 00 bd nv‑BdiZc 1
42 0018 10 1 BPL 0018 00 c0 00 bd nv‑BdiZc 1
34 4015 40 0 0015 10 c0 00 bd nv‑Bdizc 1
34 4015 10 0 0015 10 c0 00 bd nv‑Bdizc 1
35 0015 ad 1 LDA Abs 0015 10 c0 00 bd nv‑Bdizc 1
35 0015 ad 1 LDA Abs 0015 10 c0 00 bd nv‑Bdizc 1
36 0016 02 1 0016 10 c0 00 bd nv‑Bdizc 1
36 0016 02 1 0016 10 c0 00 bd nv‑Bdizc 1
37 0017 20 1 0017 10 c0 00 bd nv‑Bdizc 1
37 0017 20 1 0017 10 c0 00 bd nv‑Bdizc 1
38 2002 00 1 0018 10 c0 00 bd nv‑Bdizc 1
38 2002 00 1 0018 10 c0 00 bd nv‑Bdizc 0
39 2002 00 1 0018 00 c0 00 bd nv‑BdiZc 0
39 2002 00 1 0018 00 c0 00 bd nv‑BdiZc 0
40 c000 e0 1 0018 00 c0 00 bd nv‑BdiZc 0
40 c000 e0 1 0018 00 c0 00 bd nv‑BdiZc 0
41 2002 00 1 0018 e0 c0 00 bd Nv‑Bdizc 1
41 2002 00 1 0018 e0 c0 00 bd Nv‑Bdizc 1
42 0018 10 1 BPL 0018 00 c0 00 bd nv‑BdiZc 1
42 0018 10 1 BPL 0018 00 c0 00 bd nv‑BdiZc 1
At cycle 38, read $2002 has gone on the bus and RDY is asserted. Then in cycle 40 the DMC DMA happens. Then cycle 41, read $2002 goes back on the bus.
The pattern above is identical regardless of the address being read, obviously...so it makes me think that the above pattern is representative of the $4016/$4017 extra reads.