problem with Bregalad's midscanline demo

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problem with Bregalad's midscanline demo
by Zepper on 2012-05-20 (#94131)

Really, I need help. I rewrote the PPU timing code and the problem persists.

Zepper wrote:

- It seems the same problem with this demo by Bregalad.

This glitch occurs in my emulator at the pre-rendered scanline, since the PPU frame can be 1 cycle shorter in odd frames (340). It can be "fixed" if manually setting up the number of cycles to 339 for the pre-rendered scanline.

by Dwedit on 2012-05-20 (#94144)

What are the timestamps (in ppu pixels) for the relevant bankswitch or ppu control instructions?

The critical point is the two tile fetches at ppu pixel 5 and 7 (within the 8-cycle repeating sequence). If the CPU write that triggers bankswitching completes before the two fetches happen, you get the wrong tiles.

by Zepper on 2012-05-20 (#94149)

Dwedit wrote:
What are the timestamps (in ppu pixels) for the relevant bankswitch or ppu control instructions?

Here. (6kb)

The first hexa number with 4 digits is the PPU address (loopy_v) used.

L = scanline number, my 1st visible scanline is 21, VBlank starts at scanline zero.
C = PPU cycle (or dot).

I included the frame number and its situation: good (no glitches) and bad. The 12nd frame is good.