I see it mentioned a few times -- the RDY line is pulled low in some situations.
What is the RDY line? What does it do, and how does it work?
I cannot seem to find documentation about it in the wiki.
Bisqwit wrote:
I see it mentioned a few times -- the RDY line is pulled low in some situations.
What is the RDY line? What does it do, and how does it work?
I cannot seem to find documentation about it in the wiki.
It is a signal that will hold the CPU idle at its next read cycle if asserted. In real 6502 it is pinned externally, but in the 2A03 it is not -- but the DMA controller in the 2A03 uses it to keep the 6502 core off the bus while it does transfers for APU or PPU DMA.
Thank you for the answer.
When the CPU does a RAM access, or it accesses one of its internal registers, where does the address go? Does e.g the cartridge, or the PPU, see that the CPU is now reading or writing its RAM?
Does the RDY line prevent the CPU from reading the RAM?
Bisqwit wrote:
Thank you for the answer.
When the CPU does a RAM access, or it accesses one of its internal registers, where does the address go? Does e.g the cartridge, or the PPU, see that the CPU is now reading or writing its RAM?
Does the RDY line prevent the CPU from reading the RAM?
Here's the information from page 37 of the
Synertek 6502 manual:
Extra wide image |
Text version
EDIT: Thanks for the image edit...I realized the image was gigantic but had to rush out the door to get to work before I could fix it!
The CPU puts addresses on the CPU address bus. The cartridge sees A14-A0 and PRG /CE, the latter of which is generated from A15 and a modified Phi2. The cart can watch writes to PPU registers ($2000-$3FFF) and writes to internal RAM ($0000-$1FFF), but trying to override anything internal and readable ($0000-$1FFF, $2xx2, $2xx4, and $2xx7) will cause a bus conflict. And I seem to remember that carts can see the data bus during APU writes ($4010-$401F) and allow reading any anywhere that isn't ordinarily readable; it has been suggested to use this for a readable register at $4011 for heavy DAC wizardry.
The PPU can't see most of the CPU address bus. All it can see are the CPU's data bus, the B bus (low three bits of the address bus), an enable signal constructed from A15-A13, and (I think) R/W.
As for how RDY works, consult the 6502 datasheet.
