Can't figure out Blargg APU test failure

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Can't figure out Blargg APU test failure
by jwdonal on 2011-06-25 (#80544)
Hello all,

I'm having some trouble with one of Blargg's APu test ROMs. Specfically, the irq_flag single test in this ZIP: http://blargg.parodius.com/nes-tests/apu_test.zip

No matter what I do I always get error #4 but I have looked at the logic analyzer trace in my emu and the flag is definitely being set.

What's more interesting is that if I run the irq_flag single test from this ZIP it passes no problems: http://www.slack.net/~ant/nes-tests/bla ... .07.30.zip

Fortunately, Blargg graciously provided the full source for both tests. But in comparing the source for the two #4 cases in both irq_flag ROMs they are identical from what I can tell (except that he uses a 'jeq' macro in the one that fails instead of a 'beq' instrux when checking for pass/fail).

Can anyone help me? I have tried almost everything I can think of. I'm going to try one more thing but if that doesn't work I'm out of ideas...

by jwdonal on 2011-06-25 (#80563)
Okay, so I've traced this out some more on my logic analyzer. In the test ROM that does _not_ work the following occurs:

1) APU IRQ flag is set
2) "delay_msec 20" macro expires a short time later
3) The CPU's IRQ-disable bit in the PS register gets cleared from a PLP operation
4) CPU IRQ cycle starts (since APU IRQ flag is set)
5) The CPU IRQ routine executes BIT $4015 which clears the APU IRQ flag
6) RTI occurs
7) "JSR should_be_set" occurs
8) Executes LDA $4015 and receives $00 (since the APU IRQ flag was already cleared in step 5).

So what is wrong with this picture? Is the APU IRQ flag supposed to be set again after being cleared in Step 5 or something?? At least now I see why it's not working but it makes no sense at all. I thought any read to $4015 should clear the APU IRQ flag....??

In the test ROM that does work, steps 3 through 6 never occur. So there is no problem.

by jwdonal on 2011-06-26 (#80569)
Ummm...yeah....so this turned out to be a major bug in my CPU. The IRQ routine in steps 4 through 6 never should have been occurring. My CPU's PS register was getting corrupted in step 3 (i.e. the interrupt flag never should have been cleared). Doh! :-o

I fixed the CPU bug and the test passes now. So I was able to get another test ROM working _and_ I fixed a nasty CPU bug simultaneously. Yey! :)

by Zepper on 2011-06-26 (#80573)
Heh, just to avoid a forever alone here. :) My emu is ok with that test, but it fails with 5_len_timing.nes ;)