Scripted mapper plugins

var shiftValue = 0; // Holds the shift register value
var bitCount = 0; // Counts how many bits have been written
var latch = 0; // Is set to shiftValue when it has 5 bits
var latchFull = 0; // Flag determining if the latch has just been loaded
var mirroring = 0; // mirroring behavior
var prgMode = 0; // PRG bank behavior
var chrMode = 0; // CHR bank behavior (flag)
var chrBankA = 0; // PPU $0000-0FFF or $0000-1FFF bank
var chrBankB = 0; // PPU $1000-1FFF bank
var prgBank = 0; // PRG bank
var ramDisabled = 0; // Flag determining if cart RAM is disabled

// Evaluate the shift register behavior first.
on CPU_Write:8000,FFFF {
  if !(PRG_Data & 0x80) {
    shiftValue = shiftValue << 1;
    shiftValue |= PRG_Data & 1;
    bitCount++;
    if (bitCount == 5) {
      latch = shiftValue & 0x1F;
      bitCount = 0;
      latchFull = 1;
    }
  } else {
    bitCount = 0;
  }
}

// Afterwards, check which address range was written to.
// The appropriate code only runs when the latch has been freshly loaded from
// the previous routine.

on CPU_Write:8000,9FFF { // Control register
  if (latchFull) {
    latchFull = 0;
    mirroring = latch & 3;
    prgMode = (latch >> 2) & 3;
    chrMode = latch & 0x10; // Only need to know if this is zero or nonzero
  }
}

on CPU_Write:A000,BFFF { // CHR Bank A (0000-0FFF or 0000-1FFF)
  if (latchFull) {
    latchFull = 0;
    chrBankA = latch << 12; // %b bbbb.... ........
  }
}

on CPU_Write:C000,DFFF { // CHR Bank B (1000-1FFF)
  if (latchFull) {
    latchFull = 0;
    chrBankB = latch << 12; // %b bbbb.... ........
  }
}

on CPU_Write:E000,FFFF { // PRG Bank (8000-FFFF or 8000-BFFF or C000-FFFF)
  if (latchFull) {
    latchFull = 0;
    prgBank = (latch & 0xF) << 14; // %bb bb...... ........
    ramDisabled = latch & 0x10; // Only need to know if this is zero or nonzero
  }
}

// Cart RAM
on CPU_Read:6000,7FFF {
  if !(ramDisabled) {
    PRG_Data = PRG_RAM_Space[CPU_Addr & 0x1FFF];
  }
  // Assume open bus if PRG_Data isn't set during a read operation.
}


// PRG Banks
on CPU_Read:8000,BFFF {
  switch (prgMode) {
  case 0: // PRG Bank 8000-FFFF, ignore lowest bit
  case 1: // CPU_Addr will fill that in, actually
    PRG_Data = PRG_Space[(prgBank & 0x38000) | CPU_Addr];
    break;
  case 2: // PRG Bank 8000-BFFF
    PRG_Data = PRG_Space[prgBank | (CPU_Addr & 0x3FFF)];
    break;
  case 3: // 8000-BFFF fixed to first bank
    PRG_Data = PRG_Space[CPU_Addr & 0x3FFF];
    break;
  }
}
on CPU_Read:C000,FFFF {
  switch (prgMode) {
  case 0: // PRG Bank 8000-FFFF, ignore lowest bit
  case 1: // CPU_Addr will fill that in, actually
    PRG_Data = PRG_Space[(prgBank & 0x38000) | CPU_Addr];
    break;
  case 2: // C000-FFFF fixed to last bank
    PRG_Data = PRG_Space[CPU_Addr | 0x3C000];
    break;
  case 3: // PRG Bank C000-FFFF
    PRG_Data = PRG_Space[prgBank | (CPU_Addr & 0x3FFF)];
    break;
  }
}

// CHR Banks
on PPU_Read:0000,0FFF {
  if (chrMode) { // nonzero == low bit considered
    PPU_Data = PPU_Space[chrBankA | (PPU_Addr & 0x0FFF)];
  } else { // zero == low bit ignored (let PPU_Addr fill it in)
    PPU_Data = PPU_Space[(chrBankA & 0x1E000) | PPU_Addr];
  }
}
on PPU_Write:0000,0FFF {
  if (chrMode) { // nonzero == low bit considered
    PPU_Space[chrBankA | (PPU_Addr & 0x0FFF)] = PPU_Data;
  } else { // zero == low bit ignored (let PPU_Addr fill it in)
    PPU_Space[(chrBankA & 0x1E000) | PPU_Addr] = PPU_Data;
  }
}
on PPU_Read:1000,1FFF {
  if (chrMode) { // nonzero == use chrBankB
    PPU_Data = PPU_Space[chrBankB | (PPU_Addr & 0x0FFF)];
  } else { // zero == use chrBankA and let PPU_Addr fill in low bit
    PPU_Data = PPU_Space[(chrBankA & 0x1E000) | PPU_Addr];
  }
}
on PPU_Write:1000,1FFF {
  if (chrMode) { // nonzero == use chrBankB
    PPU_Space[chrBankB | (PPU_Addr & 0x0FFF)] = PPU_Data;
  } else { // zero == use chrBankA and let PPU_Addr fill in low bit
    PPU_Space[(chrBankA & 0x1E000) | PPU_Addr] = PPU_Data;
  }
}

// Nametable mirroring
on PPU_Read:2000,23FF { // Upper Left
  switch (mirroring) {
  case 0: // 1 Screen A
  case 2: // Vertical
  case 3: // Horizontal
    PPU_Data = CIRAM[PPU_Addr & 0x3FF];
    break;
  case 1: // 1 Screen B
    PPU_Data = CIRAM[(PPU_Addr & 0x3FF) | 0x400];
    break;
  }
}
on PPU_Write:2000,23FF { // Upper Left
  switch (mirroring) {
  case 0: // 1 Screen A
  case 2: // Vertical
  case 3: // Horizontal
    CIRAM[PPU_Addr & 0x3FF] = PPU_Data;
    break;
  case 1: // 1 Screen B
    CIRAM[(PPU_Addr & 0x3FF) | 0x400] = PPU_Data;
    break;
  }
}
on PPU_Read:2400,27FF { // Upper Right
  switch (mirroring) {
  case 0: // 1 Screen A
  case 3: // Horizontal
    PPU_Data = CIRAM[PPU_Addr & 0x3FF];
    break;
  case 1: // 1 Screen B
  case 2: // Vertical
    PPU_Data = CIRAM[(PPU_Addr & 0x3FF) | 0x400];
    break;
  }
}
on PPU_Write:2400,27FF { // Upper Right
  switch (mirroring) {
  case 0: // 1 Screen A
  case 3: // Horizontal
    CIRAM[PPU_Addr & 0x3FF] = PPU_Data;
    break;
  case 1: // 1 Screen B
  case 2: // Vertical
    CIRAM[(PPU_Addr & 0x3FF) | 0x400] = PPU_Data;
    break;
  }
}
on PPU_Read:2800,2BFF { // Lower Left
  switch (mirroring) {
  case 0: // 1 Screen A
  case 2: // Vertical
    PPU_Data = CIRAM[PPU_Addr & 0x3FF];
    break;
  case 1: // 1 Screen B
  case 3: // Horizontal
    PPU_Data = CIRAM[(PPU_Addr & 0x3FF) | 0x400];
    break;
  }
}
on PPU_Write:2800,2BFF { // Lower Left
  switch (mirroring) {
  case 0: // 1 Screen A
  case 2: // Vertical
    CIRAM[PPU_Addr & 0x3FF] = PPU_Data;
    break;
  case 1: // 1 Screen B
  case 3: // Horizontal
    CIRAM[(PPU_Addr & 0x3FF) | 0x400] = PPU_Data;
    break;
  }
}
on PPU_Read:2C00,2FFF { // Lower Right
  switch (mirroring) {
  case 0: // 1 Screen A
    PPU_Data = CIRAM[PPU_Addr & 0x3FF];
    break;
  case 1: // 1 Screen B
  case 2: // Vertical
  case 3: // Horizontal
    PPU_Data = CIRAM[(PPU_Addr & 0x3FF) | 0x400];
    break;
  }
}
on PPU_Write:2C00,2FFF { // Lower Right
  switch (mirroring) {
  case 0: // 1 Screen A
    CIRAM[PPU_Addr & 0x3FF] = PPU_Data;
    break;
  case 1: // 1 Screen B
  case 2: // Vertical
  case 3: // Horizontal
    CIRAM[(PPU_Addr & 0x3FF) | 0x400] = PPU_Data;
    break;
  }
}