James wrote:
Does access to the CPU I/O registers (e.g., APU registers or OAM DMA) show up on the address bus?
Yes, they do show up. On the HardNES player I made ages ago, I mapped RAM under 4xxxh so that I could read back what was written to the registers. This worked fine.
The only caveat is on readback registers (4015) you will get the bits from 4015 instead of from the outside world. For the unimplemented bits of 4015 I am not sure what happens. They either come from the outside world or are set to a default level (0 or thereabouts).
Also it was brought up that 4018, 4019, and 401a are actually readable too and return the square volume and/or DPCM level somehow but I am not sure if it works. Q messaged me on IRC one day and said he thinks after studying the chips that this might happen.
Unfortunately my copyNES doesn't work any more due to a parallel port problem after I replaced the mobo on PC #2 so I have not checked yet.