[As small note, the following represents an emulation point of view, an abstraction layer over the true hardware operation.]
- What's the timing diagram of a DMC DMA? Let's say there's a DMC DMA ready and it'll take 4 CPU cycles.
1. The CPU is suspended by 4 CPU cycles. Is the APU clocked? Plus, during this time, the PPU should run for 3x4 = 12 PPU cycles (NTSC) before the DMA starts, but is this correct?
EDIT: looks like it's true.
2. Once the DMC DMA is complete, is the DMC immediately clocked?
EDIT: nothing stops the DMC to be clocked, as it seems so.
3. After clocking the DMC, the sample buffer is empty and DMC length counter is not zero. Does the DMA occur in the next CPU cycle or does the memory fetch occur immediately after that?
EDIT2: it occurs in the next CPU cycle.
- What's the timing diagram of a DMC DMA? Let's say there's a DMC DMA ready and it'll take 4 CPU cycles.
1. The CPU is suspended by 4 CPU cycles. Is the APU clocked? Plus, during this time, the PPU should run for 3x4 = 12 PPU cycles (NTSC) before the DMA starts, but is this correct?
EDIT: looks like it's true.
2. Once the DMC DMA is complete, is the DMC immediately clocked?
EDIT: nothing stops the DMC to be clocked, as it seems so.
3. After clocking the DMC, the sample buffer is empty and DMC length counter is not zero. Does the DMA occur in the next CPU cycle or does the memory fetch occur immediately after that?
EDIT2: it occurs in the next CPU cycle.