cpu_timing_test6 by Blargg

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cpu_timing_test6 by Blargg
by cmoh89 on 2011-02-27 (#74716)
The read me said to post Unknown Erros to the forum, so the following is the error I'm getting when testing my emulation.


6502 Timing Test (16 Seconds)
Official Instructions Only
Fail OP :$00
Unknown Error
$019B

If you have any advice/knowledge on what could possibly be wrong with my emulation that would cause this error, that would be great if you could share that to me.

by Zepper on 2011-02-27 (#74730)
- It's the BRK. Do you know the BRK timing diagram?
Code:
        1    PC     R  fetch opcode, increment PC
        2    PC     R  read next instruction byte (and throw it away),
                       increment PC
        3  $0100,S  W  push PCH on stack, decrement S
        4  $0100,S  W  push PCL on stack, decrement S
        5  $0100,S  W  push P on stack (with B flag set), decrement S
        6   $FFFE   R  fetch PCL
        7   $FFFF   R  fetch PCH

by cmoh89 on 2011-03-20 (#75647)
I do not know the BRK timing diagram. Can you point me in the right direction to find more infomation about it?

by Zepper on 2011-03-22 (#75681)
Perhaps I wasn't crystal clear. Look at my message: it has how the BRK works, cycle by cycle (first column at left).

by cmoh89 on 2011-03-22 (#75684)
Thank you. I didn't understand what the code was representing originally. Now, it makes sense to me.

by cartlemmy on 2011-03-22 (#75687)
Zepper wrote:
...the BRK timing diagram


That's pretty cool, is there similar diagrams for all the instructions, or did you just create this for this case?

by tepples on 2011-03-22 (#75688)
I don't know about the 6502 data sheet (don't have it in front of me), but the 65C816 data sheet that I often referred to back when I coded for an Apple IIGS has similar diagrams.

by albailey on 2011-03-22 (#75689)
About halfway down this document it looks to describe most of what is wanted:

http://nesdev.com/6502_cpu.txt

Al

by Hamburgler on 2011-03-22 (#75693)
Also useful:

http://users.telenet.be/kim1-6502/6502/hwman.html#AA
Appendix A - SUMMARY OF SINGLE CYCLE EXECUTION