I discovered an incredibly nasty bug in my PPU design last night (thanks to one of Blargg's test ROMs). This bug has to do with the PPU's control register interface (i.e. the interface that the CPU uses to manage/observe the state of the PPU). This bug got me thinking about something semi-related, which I hadn't even really thought about until now...
If the PPU clock runs exactly 3 times faster than the CPU clock, then doesn't that mean that for every assertion of the PPU's chip-select line (i.e. the CPU wants to read/write a PPU register), that the PPU *internally* would actually perform that read/write 3 times in a row before the CPU was even able to deassert chip-select?
If the PPU clock runs exactly 3 times faster than the CPU clock, then doesn't that mean that for every assertion of the PPU's chip-select line (i.e. the CPU wants to read/write a PPU register), that the PPU *internally* would actually perform that read/write 3 times in a row before the CPU was even able to deassert chip-select?