So I found blargg_apu_2005.07.30 test ROM package yesterday. Hopefully this is the latest. I went from passing no tests [I expected this...my APU had been PPU-frame-based!]
I now pass tests 01, 02, 03, 04, 05, 06, 07, and 09.
I believe I have a clear path toward passing the other three, I just haven't completely got there yet.
I'm curious about a couple of things.
1. Does the APU still run if the CPU is being consumed by PPU sprite DMA fetches? Or does it get held off also? Seeing as the APU is internal and doesn't need to do memory fetches unless it is doing DMA itself, I believe it should be operational throughout a PPU sprite DMA. Either way I could put together a pretty simple test ROM to test this...I just don't know which way it goes.
2. The test.txt document notes for test 08 suggest "IRQ handler is invoked at minimum 29833 clocks after writing $00 to $4017." But the readme.txt shows IRQ being *generated* by the APU on cycles 29830, 29831, and 29832. Given an IRQ takes *at least* 7 CPU cyles to get into, how is it possible? Looking at the test source it *is* expecting the IRQ to fire.
I now pass tests 01, 02, 03, 04, 05, 06, 07, and 09.
I believe I have a clear path toward passing the other three, I just haven't completely got there yet.
I'm curious about a couple of things.
1. Does the APU still run if the CPU is being consumed by PPU sprite DMA fetches? Or does it get held off also? Seeing as the APU is internal and doesn't need to do memory fetches unless it is doing DMA itself, I believe it should be operational throughout a PPU sprite DMA. Either way I could put together a pretty simple test ROM to test this...I just don't know which way it goes.
2. The test.txt document notes for test 08 suggest "IRQ handler is invoked at minimum 29833 clocks after writing $00 to $4017." But the readme.txt shows IRQ being *generated* by the APU on cycles 29830, 29831, and 29832. Given an IRQ takes *at least* 7 CPU cyles to get into, how is it possible? Looking at the test source it *is* expecting the IRQ to fire.