Hi, I'm using the doc "Documentation for the NMOS 65xx/85xx Instruction Set" by John West and Marko Mäkelä, for accurate instruction timing, dummy reads and writes, etc.
In one addressing mode, it says:
What is the latch? should I care from the emulation standpoint, I.E. does it have a side effect, or can I just use a temp variable to hold the value and have no further effects?
In one addressing mode, it says:
Code:
Absolute indirect addressing (JMP)
# address R/W description
--- --------- --- ------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R fetch pointer address low, increment PC
3 PC R fetch pointer address high, increment PC
4 pointer R fetch low address to **latch**
5 pointer+1* R fetch PCH, copy latch to PCL
# address R/W description
--- --------- --- ------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R fetch pointer address low, increment PC
3 PC R fetch pointer address high, increment PC
4 pointer R fetch low address to **latch**
5 pointer+1* R fetch PCH, copy latch to PCL
What is the latch? should I care from the emulation standpoint, I.E. does it have a side effect, or can I just use a temp variable to hold the value and have no further effects?