APU Frame Sequencer Question

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APU Frame Sequencer Question
by jwdonal on 2010-02-23 (#56985)
In Brad Taylor's NESSOUND document http://nesdev.com/NESSOUND.txt it states:

"During count sequences 0..3, the linear (triangle) and envelope decay (square & noise) counters recieve a clock for each count. This means that both these counters are clocked once immediately after $4017.7 is written with a value of 1."

And in Blargg's APU reference doc http://nesdev.com/apu_ref.txt it states:

"If the mode flag is clear, the 4-step sequence is selected, otherwise the
5-step sequence is selected and the sequencer is immediately clocked once."

It seems like there is something "special" about the 5-step sequence (mode 1) and ensuring that it is clocked *immediately*, but I can't figure out what it is. If you look at the following diagram in Blargg's document, the envelope and linear counters (specified with the 'e') get updated in both 4-step mode and 5-step mode *immediately* in step 0. What is so special about the 5-step mode??

Code:
    f = set interrupt flag
    l = clock length counters and sweep units
    e = clock envelopes and triangle's linear counter

mode 0: 4-step  effective rate (approx)
---------------------------------------
    - - - f      60 Hz
    - l - l     120 Hz
    e e e e     240 Hz

mode 1: 5-step  effective rate (approx)
---------------------------------------
    - - - - -   (interrupt flag never set)
    l - l - -    96 Hz
    e e e e -   192 Hz


In other words, as I understand it, if I write a 0 to $4017.7, then the envelope and linear counters will be immediately updated for the 4-step mode (as shown above). And if I write a 1 to $4017.7, then the envelope, linear counters, length and sweep units will all be immediately updated for the 5-step mode (as shown above). So whether you write a 0 or a 1 to 4017.7, both modes have some "immediate" effect......so what's the big deal about stressing the 5-step mode?

------

And one more question while I'm at it - this might have something to do with the above question but I can't be sure. Does anyone know why Brad Taylor specifies the following counter sequence for mode 0?

Code:
$4017.7  sequence
-------  --------
0        4, 0,1,2,3, 0,1,2,3,..., etc.
1        0,1,2,3,4, 0,1,2,3,4,..., etc.


It seems like Brad is trying to say that you should not clock the envelope or linear counters when you initially write 0 to $4017.7 (since a step #4 in mode 0 doesn't even exist). Funny thing about this is that Blargg doesn't mention anything about this 1 cycle "delay" for mode 0 in his document, which is adding to my confusion. :)

Thanks for the help!!

P.S. My website is finally back up now! https://rm-rfroot.net/nes_fpga/

by blargg on 2010-02-24 (#57017)
First off, you'd best ignore everything except apu_ref or the Wiki. The other is much older and has many errors. Imagine you had a perfect APU reference, and the current ones. If you kept comparing the two, you'd waste time finding errors in the current ones. I'm not saying my apu_ref or the Wiki are perfect, just that they are the most current ones.

Take a look at the Wiki page about the frame sequencer. Note how it reloads the divider in either case, but clocks immediately only for the 5-step mode.
i think i get it
by jwdonal on 2010-02-24 (#57048)
Ok, I think I understand...lemme try implementing this and I'll see how it works out.

And I tend agree with you're documentation comment. I didn't know that Brad's APU doc had so many errors in it. From my experience so far (with writing the CPU and PPU) the best thing that I have found to do is come to a majority vote from all available documentation rather than just picking one. But I will disregard Brad's APU doc from this point forward since you are obviously one of the resident APU experts. :)

Thanks!!

by tepples on 2010-02-24 (#57049)
A wiki with a healthy Recent Changes (with some edits in the past month and not dominated by spam bots) will tend to be more accurate because unlike a static document that has already been published, it can incorporate new discoveries about the hardware. One common scenario is that someone reports findings on the BBS or the IRC channel, and then someone else goes in and explains it on the wiki within the day.

by jwdonal on 2010-12-28 (#72086)
I'm back to working on my emu's APU now. I wanted to bump this thread as opposed to starting a new one.

Code:
mode 1: 5-step  effective rate (approx)
---------------------------------------
       - - - - -   (interrupt flag never set)
       l - l - -    96 Hz
       e e e e -   192 Hz
Step#: 0 1 2 3 4


So I understand that if a write to $4017 occurs and bit 7 is '1', then I need to immediately clock both the [length and sweep units (identified as 'l')] and the [envelope and triangle units (identified as 'e')].

My question is, after that immediate clock, is the next step count supposed to be #0 (i.e. both 'l' and 'e' would be clocked again) or is the next step count supposed to be #1 (i.e. only 'e' would be clocked).

Thanks!

UPDATE: Blargg's apu_ref.txt states: "On a write to $4017, the divider and sequencer are reset...". So therefore, if the sequencer is set to 5-step mode, then both 'e' and 'l' are clocked immediately, and the step number is also reset back to 0. Which means at the next 240Hz clock both 'e' and 'l' would be clocked again. Hope I've got that right....