PPU clarifications

I've some trouble emulating the PPU in my
emulator and hope that I can get some help
and clarifications on some things from you guys here.

1)
How does bit 3-4 in PPU register $2001 work?
I understand that they control if background/sprites
should be rendered, but how do they effect the PPU?
They seem to effect PPU's memory reads and if the
address (Loopy_v) should be updated with the temp
address (Loopy_t).

What is done and what is not done by the PPU
depending on how these bits are set?


2)
When is the VBlank flag set (bit 7 in $2002)?
Is it on the last cycle in the scanline after
the 240 visible or on the first cycle in PPU's
VBlank period?

Is NMI generated at the same cycle the flag is set?


3)
At which cycle in the dummy scanline is the PPU address

(Loopy_v) loaded with the temp address (Loopy_t)?

Any help appreciated.

1)

If either one of the bits is on... the PPU is active and rendering pixels normally throughout the frame. If D3 is off, every background pixel will be transparent (so the background will not be visible), and if D4 is off, every sprite pixel will be transparent (so sprites will not be visible).

If BOTH bits are off, the PPU is "turned off" and becomes inactive during frame rendering time. When the PPU is off, it will not change Loopy_V at all like it normally would if it was switched on. Games will switch off the PPU for large drawing routines... when all the drawing can't be done in VBlank. For frames which the PPU is switched off... you render pixels based on palette entry 0 (ppu$3F00).. UNLESS the PPU address (Loopy_V) is pointing to a place in palette mem ($3Fxx or any mirrored region) -- in which case you render the color the PPU address points to (many Camerica games rely on this to quickly change the background color -- most notably Micro Machines and Bee 52)


2)

VBlank flag is set at the very start of the first scanline of VBlank. For a visual example... one frame consists of the following:



The VBlank flag is raised, presumably on cycle 0 of the first scanline on that chart.

NMI is triggered AFTER VBlank is raised... there is some latency between the two. I don't know how much latency exactly, but running 1 CPU instruction between the time $2002.7 is raised and when NMI is triggered works nicely.


3)
Cycle 304. Note this reload only happens if the PPU is switched on (D3 or D4 of $2001 on). If the PPU is off, the address will not reload.

Reference:
http://nesdev.com/bbs/viewtopi ... t=304#3288

Actually, there is no latency at all on the real hardware, but you will need SOME latency if you do not emulate the CPU and PPU completely synchronously with each other (cycle for cycle).

I see... like the VBlank flag could be raised in the middle of an "LDA $2002" instruction ... but the NMI won't happen until after the instruction completes... right?