Sorry for multiple forum posts but I really don't know where else to ask these kinds of questions. This question is in reference to the below text:
I completely understand the table bitmap section. What I'm confused about is the palette select data, and how that is handled. Each tile fetch phase has 4 parts:
That of course is the full 8cc cycle for each tile. When is the PPU supposed to be doing this palette select thing? I know I've read in a doc that says the PPU never makes a fetch for palette data on the address bus, which would obviously mean that the fetch is internal during rendering. Does it simply do this while doing the other 4 fetches?
My other question is really two combined..
The first fetched tile is really the 3rd tile in the scanline. I also noticed that since the pattern data is being put at the end of 16-bit shift registers, they will only be usable for 8 cycles (the time it takes to fetch another tile). Does this mean that while the PPU is reading in these values, it is also acting on the bit0 values of the four latches and actively rendering to something? If it rendered like this, I would expect it to start rendering tile 2 on the scanline first, not tile three.
Hopefully someone can help me clear these questions up. Thanks again!
Code:
At the start of a new tile fetch phase (every 8 cc's), both latched pattern
table bitmaps are loaded into the upper 8-bits of 2- 16-bit shift registers
(which both shift right every clock cycle). The palette select data is also
transfered into another latch during this time (which feeds the serial
inputs of 2 8-bit right shift registers shifted every clock). The pixel data
is fed into these extra shift registers in order to implement fine
horizontal scrolling, since the periods when the PPU fetch tile data is
fixed.
table bitmaps are loaded into the upper 8-bits of 2- 16-bit shift registers
(which both shift right every clock cycle). The palette select data is also
transfered into another latch during this time (which feeds the serial
inputs of 2 8-bit right shift registers shifted every clock). The pixel data
is fed into these extra shift registers in order to implement fine
horizontal scrolling, since the periods when the PPU fetch tile data is
fixed.
I completely understand the table bitmap section. What I'm confused about is the palette select data, and how that is handled. Each tile fetch phase has 4 parts:
- Name table byte fetch
Attribute table byte fetch
Pattern table bitmap #0 fetch
Pattern table bitmap #1 fetch
That of course is the full 8cc cycle for each tile. When is the PPU supposed to be doing this palette select thing? I know I've read in a doc that says the PPU never makes a fetch for palette data on the address bus, which would obviously mean that the fetch is internal during rendering. Does it simply do this while doing the other 4 fetches?
My other question is really two combined..
The first fetched tile is really the 3rd tile in the scanline. I also noticed that since the pattern data is being put at the end of 16-bit shift registers, they will only be usable for 8 cycles (the time it takes to fetch another tile). Does this mean that while the PPU is reading in these values, it is also acting on the bit0 values of the four latches and actively rendering to something? If it rendered like this, I would expect it to start rendering tile 2 on the scanline first, not tile three.
Hopefully someone can help me clear these questions up. Thanks again!