Memblers wrote:
$4015 can be used to re-trigger DPCM (not to pause though). But yeah it's like Bregalad said, a lot of stuff takes effect when those upper registers for each channel are changed.
I saw that mentioned in a few docs, but nothing about the rest of the channels.
Instead of making a bunch of threads, maybe I should just keep asking questions in this thread (and re-title it)?
The triangle channel is driving me a bit nuts too:
Quote:
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Linear Counter
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The Linear Counter serves as a second more-accurate duration counter for the
triangle channel. It contains a counter and an internal halt flag.
Register $4008 contains a control flag and reload value:
crrr rrrr control flag, reload value
Note that the bit position for the control flag is also mapped to a flag in the
Length Counter.
When register $400B is written to, the halt flag is set.
When clocked by the frame sequencer, the following actions occur in order:
1) If halt flag is set, set counter to reload value, otherwise if counter
is non-zero, decrement it.
2) If control flag is clear, clear halt flag.
When $400b is written to, the halt flag is set!? What halt flag is it referring to? Is is the halt flag in $4015? Also, why don't some of these docs include the values of the control bits; like bit #8 1=disable blah : 0=enable such and such. It's driving me made.
So my question is for the triangle channel. There's a linear counter and there's a length counter (pulled from the table). At what point is what enabled/used?
If bit #8 of $4008 is set, then I take the lower 7 bits and use then as literal/linear counter (and the linear counter used 240hz clock include if the 120hz clock of the length counter decrementer).
So what happens if Bit #8 is clear? The lower 7bits are ignored and the channels doesn't become active until I write a new value to reg $400b in which the upper 5bits are the index into the length counter? Then the channels goes active?