Quick PPU question - At which PPU clock does Y scroll increment?
(trying to get rid of a shaky status bar...)
Okay, I'll alter my post...
Kick Master does its second 2006 write anywhere between pixel clock 247 and 272. Then it does two 2005 writes. PPU $2001 = 0E. Why doesn't the status bar shake?
Managed to figure out what's going on...
PPU clock 251 is the clock when Y scroll is incremented.
Any STA $2006 instruction will take at least 9 PPU cycles before the actual memory write happens. So pixel clock 242 and up are safe times to start writing a new scrolling location.
I had my timing screwed up a bit, forgot to multiply by 3, so I was giving a clearance of 3 cycles instead of 9.
A write to a register typically doesn't change behavior until after the write cycle is complete. For example, in the case of STA $2006, the write cycle is the fourth cycle of the opcode, so the effect will not happen until the fourth cycle is completed. Reads take effect sooner (probably about 1/2 of a CPU cycle, since that's how long the Phi-2 line is high). Nestopia deals with this by letting the PPU run one cycle longer for a register write than for a register read.
Dwedit wrote:
Managed to figure out what's going on...
PPU clock 251 is the clock when Y scroll is incremented.
Any STA $2006 instruction will take at least 9 PPU cycles before the actual memory write happens. So pixel clock 242 and up are safe times to start writing a new scrolling location.
I had my timing screwed up a bit, forgot to multiply by 3, so I was giving a clearance of 3 cycles instead of 9.
- Perhaps you want to read
here..?