- OK, I did a quick search here and found some old posts. I understood most of them now, but I have a few questions (NTSC):
- The CPU part (loopy_v) seems quite clear. The PPU part (A12 rising) is the point. An A12 rising occurs with the pattern table select 0000 or 1000, right?
- Someone said about only the first raise taken effect on IRQ clock. Are the others ignored?
- As already posted, if the PPU part is "ignored", the IRQ clocks at every even scanline, like 2,4,6,8,10,12... so, the PPU A12 is required to get 241 clocks in a frame, but is possible to clock twice in a scanline period, or even more than that?
- To finish off, I use an engine that starts rendering from pixel 0 (left-most) time, instead of a "bit before". Same for sprites: they're evaluated at pixel 257 (time). Could it block proper MMC3 IRQ emulation somewhat?
- The CPU part (loopy_v) seems quite clear. The PPU part (A12 rising) is the point. An A12 rising occurs with the pattern table select 0000 or 1000, right?
- Someone said about only the first raise taken effect on IRQ clock. Are the others ignored?
- As already posted, if the PPU part is "ignored", the IRQ clocks at every even scanline, like 2,4,6,8,10,12... so, the PPU A12 is required to get 241 clocks in a frame, but is possible to clock twice in a scanline period, or even more than that?
- To finish off, I use an engine that starts rendering from pixel 0 (left-most) time, instead of a "bit before". Same for sprites: they're evaluated at pixel 257 (time). Could it block proper MMC3 IRQ emulation somewhat?
