Hi all,
According to the wiki, writting any MMC1 register with a value whose highest bit is set makes the control register to be ORed with 0x0C. As far as I understand it, this only affects CHR-ROM bank mode, as PRG-ROM bits are left untouched. The point here is that I don't see why the wiki states, literally, "..locking PRG ROM at $C000-$FFF to the last bank.". So, although the bank mode is not modified, the PRG banks are swapped while CHR banks are left intact.. Why is that?
I know MMC1 reset state is not known at all but.. would it be accurate to apply a reset shift register as MMC1's initial state?
On the other hand, I think there's a typo in "Variants" section. Shouldn't SXROM combination be "512KB of PRG ROM and 16KB of PRG RAM" instead of "512KB of PRG ROM and 32KB of PRG RAM" (as SOROM chooses between TWO 8KB banks)?
One more thing. Which exact registers and bits are "upper CHR bank select line" and "second-highest CHRbank select line" referring to in "Variants" section?
Thx.
According to the wiki, writting any MMC1 register with a value whose highest bit is set makes the control register to be ORed with 0x0C. As far as I understand it, this only affects CHR-ROM bank mode, as PRG-ROM bits are left untouched. The point here is that I don't see why the wiki states, literally, "..locking PRG ROM at $C000-$FFF to the last bank.". So, although the bank mode is not modified, the PRG banks are swapped while CHR banks are left intact.. Why is that?
I know MMC1 reset state is not known at all but.. would it be accurate to apply a reset shift register as MMC1's initial state?
On the other hand, I think there's a typo in "Variants" section. Shouldn't SXROM combination be "512KB of PRG ROM and 16KB of PRG RAM" instead of "512KB of PRG ROM and 32KB of PRG RAM" (as SOROM chooses between TWO 8KB banks)?
One more thing. Which exact registers and bits are "upper CHR bank select line" and "second-highest CHRbank select line" referring to in "Variants" section?
Thx.