I've been interested in writing emulation code for the VRC7 sound circuitry, and I'm running into a major roadblock: I can't make head or tail of *any* of Yamaha's FM chip documentation.
I have successfully written emulation code for various programmable sound generators including the 2A03 sound subsystem, the GameBoy sound subsystem, and the SN76496. All of these (as well as various other early sound chips like the AY-3-8910 and Pokey) seem to function in a roughly similar manner: the system clock is used to count down (or up) a programmable timer, and when the timer underflows (or overflows), it then clocks a logic circuit like a duty cycle generator or XOR-feedback register that creates the sound waveforms. Of course, some chips like the 2A03 incorporate additional timers that can be used to automatically update certain sound parameters at certain times, but the basic principle is similar for all of these chips. (I'd like to thank Matt Conte for assisting me with the basic principles of digital sound synthesis. Brad Taylor's documentation and Kevin Horton's technical know-how was also most helpful in obtaining a basic understanding of these circuits.)
The Yamaha YM-series FM chips *seem* wildly different. I'm not convinced they truly are. According to Vortexion's sound page: "The chips all operate in the digital domain, using adders, multipliers and look-up tables to achieve the sine wave modulation." So it seems plausible to me that the YM-series chips may simply be more complicated PSGs with more and more varied waveforms, wavetable ROMs, and timers than the old ones.
Unfortunately, the datasheets on these chips are completely incomprehensible to me. They're filled with terms both technical and musical that might as well be Greek to me. Very little documentation is provided as to what these terms mean; the sheets seem to be geared towards someone with a double major in music and advanced calculus. Nth-order Bessel functions? Detune? Key on/off? I don't know what any of this means. Has anyone written a simple explanation of how any of these chips *actually work* on a low hardware level? Something similar to Brad Taylor's NES 2A03 documentation or Kevin Horton's VRCVI info. Can anyone provide me with any help on this subject? I'm completely lost.
- Josh
I have successfully written emulation code for various programmable sound generators including the 2A03 sound subsystem, the GameBoy sound subsystem, and the SN76496. All of these (as well as various other early sound chips like the AY-3-8910 and Pokey) seem to function in a roughly similar manner: the system clock is used to count down (or up) a programmable timer, and when the timer underflows (or overflows), it then clocks a logic circuit like a duty cycle generator or XOR-feedback register that creates the sound waveforms. Of course, some chips like the 2A03 incorporate additional timers that can be used to automatically update certain sound parameters at certain times, but the basic principle is similar for all of these chips. (I'd like to thank Matt Conte for assisting me with the basic principles of digital sound synthesis. Brad Taylor's documentation and Kevin Horton's technical know-how was also most helpful in obtaining a basic understanding of these circuits.)
The Yamaha YM-series FM chips *seem* wildly different. I'm not convinced they truly are. According to Vortexion's sound page: "The chips all operate in the digital domain, using adders, multipliers and look-up tables to achieve the sine wave modulation." So it seems plausible to me that the YM-series chips may simply be more complicated PSGs with more and more varied waveforms, wavetable ROMs, and timers than the old ones.
Unfortunately, the datasheets on these chips are completely incomprehensible to me. They're filled with terms both technical and musical that might as well be Greek to me. Very little documentation is provided as to what these terms mean; the sheets seem to be geared towards someone with a double major in music and advanced calculus. Nth-order Bessel functions? Detune? Key on/off? I don't know what any of this means. Has anyone written a simple explanation of how any of these chips *actually work* on a low hardware level? Something similar to Brad Taylor's NES 2A03 documentation or Kevin Horton's VRCVI info. Can anyone provide me with any help on this subject? I'm completely lost.
- Josh