The first thing on emulation start

The first thing on emulation start
by Zepper on 2006-11-07 (#19215)

- I think the RESET. Well, it uses the exact (?) diagram of NMI and IRQ, as "read 2 dummy bytes, push PC & P onto stack...". If this is correct, so there are seven cycles and 21 PPU cycles (?). Since the screen is off by default (?), it won't mess up to the dummy scanline.
- Plus, does any CPU read/write imply 1 cycle and 3 PPU cycles?

- Could someone clarify this thing?

by tepples on 2006-11-07 (#19218)

Yes, every CPU cycle equals 3 PPU cycles.

The CPU makes a read or write on each CPU cycle. The PPU is clocked 3 times as fast as the CPU and outputs a pixel on each cycle. Thus, the PPU outputs 3 pixels for each CPU read or write.

(The above applies to Japan, North America, and Brazil. For Europe and Down Under, use a slightly larger value of 3.)

by Disch on 2006-11-07 (#19219)

tepples wrote:
(The above applies to Japan, North America, and Brazil. For Europe and Down Under, use a slightly larger value of 3.)

Right

NTSC: 1 CPU cycle = 3 PPU cycles
PAL: 1 CPU cycle = 3.2 PPU cycles

Re: The first thing on emulation start
by tokumaru on 2006-11-07 (#19223)

What about this part?
Fx3 wrote:
does any CPU read/write imply 1 cycle and 3 PPU cycles?

Is there anything like an extra cycle for reads or writes? If an instruction takes 4 cycles to execute, that's the same as 12 PPU cycles (pixels), right? Or is there any catch here?

Re: The first thing on emulation start
by tepples on 2006-11-07 (#19225)

tokumaru wrote:
If an instruction takes 4 cycles to execute, that's the same as 12 PPU cycles (pixels), right?

Correct.

Re: The first thing on emulation start
by Disch on 2006-11-07 (#19226)

tokumaru wrote:
Is there anything like an extra cycle for reads or writes?

No.

For the CPU, 1 cycle = 1 read or 1 write

Although I'm not sure what is done during all of the DMC's DMA stolen cycles, or even that extra cycle in Sprite DMA.

Quote:
If an instruction takes 4 cycles to execute, that's the same as 12 PPU cycles (pixels), right?

On NTSC, yes

Re: The first thing on emulation start
by tokumaru on 2006-11-08 (#19239)

Disch wrote:
For the CPU, 1 cycle = 1 read or 1 write

Oh, so you mean that the CPU is always reading or writing, every cycle?

by Zepper on 2006-11-08 (#19240)

Well, I'm clocking the PPU on sprite DMA extra cycle and DMC thing, or else it generates glitches.

by Disch on 2006-11-08 (#19242)

edit: Fx3 slipped in before my reply ^^

tokumaru wrote:
Oh, so you mean that the CPU is always reading or writing, every cycle?

Yes. This doc gives a good picture of what reads/writes are being performed during every cycle of each instruction.

Only times I'm not really sure about are during some of the DMC's stolen cycles and during the first (or last?) cycle of Sprite DMA -- although the CPU is probably still performing dummy reads during those times.

Also I'm not sure what effect the JAM/HLT illegal opcode has on the CPU -- it may prevent it from doing any kind of read/writes at all.

Fx3 wrote:
Well, I'm clocking the PPU on sprite DMA extra cycle and DMC thing, or else it generates glitches.

That is good. Only the CPU is suspended during sprite/dmc DMA. The PPU is still running normally.