$4017 Delay after Write Contradiction?

On this page, it says that the effects of writing to $4017 (resetting the frame counter) occur after 3 or 4 CPU cycles, but on here, it says that it occurs after 2 or 3 cycles. And then, on the same page in the following sentence, it says that the effect is immediate.

Which one is correct or am I misinterpreting what the wiki means?

Quickly looking Visual2A03, it looks like should start during the next apu_clk1 (t12848) and last until the subsequent one.

(apu_clk1 appears to be during φ1 of the CPU and the "read" phase of the APU. The frame counter either counts or restarts during apu_clk2, which is during φ1 and the "write" phase of the APU. Regardless of CPU-APU phase, "restart" is true for exactly one φ1)

Are APU "read" phases during the even CPU cycle? If so, does that mean there's either a 0 or 1 cycle delay between writing to $4017 and resetting the frame counter?

I think "read" is "even", but I'm not particularly confident. I just personally find "read" and "write" easier to remember because that's how the 2A03's DMA timing is implemented.

The pattern should go either something like

Rφ1 -
Rφ2 write to $4017
Wφ1 transfer value in → reset
Wφ2 -
Rφ1 -
Rφ2 -
Wφ1 - count

or
Wφ1 - count
Wφ2 - write to $4017
Rφ1 - transfer value in
Rφ2 -
Wφ1 - reset
Wφ2 -
Rφ1 -
Rφ2 -
Wφ1 - count

Should be able to recreate this pretty easily in Visual2A03: just track "frm_restart" and "frm_count" (and maybe apu_clk1 and apu_clk2a) with two "STA $4017,y" in memory.