VRAM access during rendering

VRAM access during rendering
by Disch on 2006-07-29 (#15792)

Just want to make sure my understanding of this is correct. I'm not really 100% on these things, and I figured I'd ask since I want to get this info in the wiki.

If my understanding is wrong, please correct me. And confirmation where I'm right would also be very helpful.

During Rendering:

* $2003 writes do nothing
* $2004 writes do nothing
* $2005 and $2006 work normally
* $2000, $2001 work normally. As does $2002.
* $2007 writes increment PPU Address like normal, but the write has no effect on VRAM (not even during HBlank)
* $2007 reads get the read buffer, then fill the read buffer with $00. PPU Address is incremented like normal.
* Writing to $4014 (being a simple macro to automate $2004 writes), does the same thing as writing to $2004 -- nothing.

by Zepper on 2006-07-30 (#15797)

-deleted-

by tepples on 2006-07-30 (#15801)

Fx3 wrote:
As far as I can tell you, sprites are evaluated after the rendering period (around cycle 257), so they're "cached" into 8-sprites buffer.

I thought they were evaluated against the scanline Y coordinate starting at x=64, and based on such evaluation, the pattern tables for sprites were fetched at x=256 through 320.

by Zepper on 2006-07-30 (#15821)

-deleted-

by dvdmth on 2006-07-31 (#15831)

Accesses to $2007 during rendering are not predictable, from what I understand, due to conflicts on the PPU address bus that come as a result. You cannot say definitively what VRAM address will be modified by $2007 writes, nor can you definitively say what the read buffer will receive on $2007 reads.

It's also my understanding that writees to $2003 and $2004 have no effect during rendering, but I don't know this for sure. Reading from $2004 is definitely valid, returning whatever OAM data is currently being examined by the sprite renderer.

by Quietust on 2006-07-31 (#15833)

dvdmth wrote:
Accesses to $2007 during rendering are not predictable, from what I understand, due to conflicts on the PPU address bus that come as a result. You cannot say definitively what VRAM address will be modified by $2007 writes, nor can you definitively say what the read buffer will receive on $2007 reads.

Accessing $2007 during rendering is quite unpredictable, as the Address Latch Enable and Read/Write signals are controlled by two independent units within the PPU - namely, the renderer and $2007 I/O. As a result, trying to use both at once results in all sorts of weird things like asserting both /Read and /Write simultaneously (which isn't too bad, since that ends up getting treated as a write) or even asserting /ALE and /Write simultaneously (which gets really messed up, since the data being written gets pushed back into the address latch, potentially resulting in another memory location being modified).