Here is my preliminary analysis.
Edit 1: Updated with krzysiobal's comment.
Edit 2: Updated with krzysiobal's final pinout, and analysis based on that.Code:
NTDEC8701 AX-24G
--------- ------
Pin# Meaning Pin# Meaning
1 PRG-A13 1 ?
2 PRG-A14 2 ?
3 PRG-A16 3 ?
4 PRG-A15 4 ?
5 CHR-A14 5 to 15
6 CHR-A11 6 PRG-A15
7 CHR-A13 7 CHR-A14
8 CHR-A12 8 CHR-A13
9 CPU-D2 9 CPU-D0
10 CPU-D3 10 CPU-D1
11 CPU-D1 11 CPU-D2
12 GND 12 GND
13 CHR-A15 13 to 16
14 CHR-A10 14 ?
15 PPU-A10 15 to 5
16 PPU-A11 16 to 13
17 PPU-A12 17 Vcc
18 CPU-D4 18 CPU-D3
19 CPU-D5 19 CPU-D4
20 CPU-D0 20 CPU-D5
21 CPU-R/W 21 CPU-R/W
22 M2 22 M2
23 PRG-!OE 23 PRG-!OE
24 CPU-ROMSEL 24 CPU-ROMSEL
25 Vcc 25 ?
26 CPU-A0 26 CPU-A0
27 CPU-A13 27 CPU-A13
28 CPU-A14 28 CPU-A14
The IC pinouts are similar enough to conclude that the IC is the same, just connected differently. Let's start with CPU D0-D5:
Code:
Jovial Race Normal
----------- ------
D5 D0
D2 D1
D0 D2
D1 D3
D3 D4
D4 D5
Jovial Race writes $01,$04,$21,$24 to $8000. The NTDEC8701 thus sees the following register numbers:
Code:
Jovial Race Normal
----------- ------
$01 $04
$04 $02
$21 $05
$24 $03
So, Jovial Race only initializes the bank registers for PPU $1000-$1FFF, at least if PPU A12 were connected normally, and no PRG register. To make these bank registers affect the entire 8 KiB CHR-ROM range and not just $1000-$1FFF,
Jovial Race connects the AX-24's PPU-A12 line (pin 17) to Vcc so that it is permanently "1". What about the bank register values?
Jovial Race writes:
Code:
$10 for 8 KiB CHR-ROM bank 0
$01 for 8 KiB CHR-ROM bank 1
$1A for 8 KiB CHR-ROM bank 2
$0B for 8 KiB CHR-ROM bank 3
OR'd with $04 to choose 32 KiB PRG-ROM bank 1.
Which means that for the bank data that
Jovial Race writes, the NTDEC8701 sees the following data:
Code:
Jovial Race Normal
----------- ------
$10 $20 for 8 KiB CHR-ROM bank 0
$01 $04 for 8 KiB CHR-ROM bank 1
$1A $38 for 8 KiB CHR-ROM bank 2
$0B $1C for 8 KiB CHR-ROM bank 3
OR'd with:
$04 $02 and for 32 KiB PRG-ROM bank 1
Now, on the Namco 108/NTDEC8701, the several CHR bank register bits (as the Namco 108 sees them) become the following CHR address bits:
Code:
$02 Normally CHR A11, pin 6, which is PRG A15 on Jovial Race.
$04 Normally CHR A12, pin 8, which is CHR A13 on Jovial Race.
$08 Normally CHR A13, pin 7, which is CHR A14 on Jovial Race.
$10 Normally CHR A14, pin 5, which Jovial Race connects to PPU-A10 (pin 15).
$20 Normally CHR A15, pin 13, which Jovial Race connects to PPU-A11 (pin 16).
As for the last two lines of the previous table,
Jovial Race's use of bits 3 and 4 (bits 4 and 5 from the IC's perspective) force the IC to think that any CHR-ROM access falls into the same 1 KiB region that is determined by the highest two bits of the bank register value (which ultimately become PPU-A10 and PPU-A11) and the permanently-high PPU-A12:
Code:
8 KiB
CHR-ROM $8001 IC CHR
bank bits bits range
------- ----- ----- -----
0 $10 $20 $1800-$1BFF
1 $00 $00 $1000-$13FF
2 $18 $30 $1C00-$1FFF
3 $08 $10 $1400-$17FF
(only bits relevant for the CHR range shown)
If the four relevant bank registers are initialized to the same value, then the two highest bank register value bits become irrelevant (which is why our dumping script variant that leaves them at zero still works). If they are not all set to the same value however, then interesting things might occur, as writing to one bank register also changes which bank register is the relevant one. At this point, I think that this must be a copy-protection measure.
To summarize: Everything checks out that
Jovial Race's AX-24G is a Namco-108-compatible NTDEC8701 connected to function like a simple GNROM-like latch. The reason for doing so must have been either that Joy Van had a surplus of these chips lying around in those early days, or as a (rather ineffective) copy-protection measure.
Thanks two million, krzysiobal and sdm! Comments and corrections welcome.