Here's an odd one. This board type is used on the two Korean cartridges specified in the thread subject, each containing a handful of "educational" minigames. It consists of an AX5202P MMC3 clone, a 74LS174, and a Programmable Logic Array (PAL) chip. I don't know for sure how this board works internally, only what the Kazzo dumping script must look like to get a usable ROM image, and how to emulate it to make it work.
Apart from the usual MMC3 registers, there is an Outer Bank register at $8010-$801F which seems to latch the four lowest address bits.The outer bank register does not simply add additional bits to the MMC3 bank registers, but instead adds a start address that is not a power of two to whatever the MMC3 is addressing. The values written to the outer bank register are only #$00, #$05, #$0A, or #$0F.
In the CPU address space, the outer bank register simply functions as an additional 16K bank number, so a value of #$05 adds a start address of 0x14000. Of course, the MMC3 bank registers 6 and 7 can be set to access an inner bank address of 0x14000+ as well with values #$0A to #$0F. These values have a special meaning: they are hard-wired to access the last outer bank, regardless of the outer bank register, so an MMC3 bank register value of #0x0A will select a bank starting at 0x3C000 (the start address of outer bank #0x0F) plus 0x14000 (the inner bank start address) = 0x50000. This means in practice that outer banks #$00, #$05, #$0A are 80K in size (because the last 48K are taken from outer bank #$0F), while outer bank #$0F is 128 KiB in size, yielding a total PRG-ROM size of 368 KiB. This is the case for both cartridges.
PPU space mapping is different. The same outer bank register also selects an outer CHR-ROM bank, but its size (for the outer bank register's step size of 5) differs between the two cartridges. In the first pack, the outer CHR bank is 96 KiB (MMC3 bank register values #$00-#$5F are valid) yielding a total CHR-ROM size of 384 KiB, while in the second pack, the outer CHR bank size is 120 KiB (MMC3 bank register values #$00-#$77 are valid) yielding a total CHR-ROM size of 480 KiB. If an MMC3 CHR bank register contains a value higher than #$5F/#$77, then the beginning of the last hard-wired outer PRG-ROM bank is mapped into PPU space! The games do not seem to rely on that feature, but it allows me to determine what the outer CHR bank size actually is. Assuming a fixed number of four outer CHR banks, the outer CHR bank size can then be detected by an emulator by simply looking at the number of 8 KiB CHR-ROM banks in the NES header. I don't know how the board actually manages to derive values of #$60 or #$78 from an outer bank register value of #$05, though.
Attached find PCB images,a Nintendulator mapper source file, and Kazzo dumping scripts for the two cartridges. I do not know the Kazzo language enough to automatically determine the outer CHR bank size by looking for the PRG-ROM data appearing in PPU address space, so each pack has its own dumping script. Compiled mapper DLL here. I have tentatively assigned mapper number 516 for this board, as it is an Asia-only release. PCB images and cartridge dumping by MLX, whose prerogative it is to release the ROM images at an appropriate place. The previous ROM images that are floating around the internet disregarded the outer bank register and are thus incomplete.
Edit: See below.
Apart from the usual MMC3 registers, there is an Outer Bank register at $8010-$801F which seems to latch the four lowest address bits.
In the CPU address space, the outer bank register simply functions as an additional 16K bank number, so a value of #$05 adds a start address of 0x14000. Of course, the MMC3 bank registers 6 and 7 can be set to access an inner bank address of 0x14000+ as well with values #$0A to #$0F. These values have a special meaning: they are hard-wired to access the last outer bank, regardless of the outer bank register, so an MMC3 bank register value of #0x0A will select a bank starting at 0x3C000 (the start address of outer bank #0x0F) plus 0x14000 (the inner bank start address) = 0x50000. This means in practice that outer banks #$00, #$05, #$0A are 80K in size (because the last 48K are taken from outer bank #$0F), while outer bank #$0F is 128 KiB in size, yielding a total PRG-ROM size of 368 KiB. This is the case for both cartridges.
PPU space mapping is different. The same outer bank register also selects an outer CHR-ROM bank, but its size (for the outer bank register's step size of 5) differs between the two cartridges. In the first pack, the outer CHR bank is 96 KiB (MMC3 bank register values #$00-#$5F are valid) yielding a total CHR-ROM size of 384 KiB, while in the second pack, the outer CHR bank size is 120 KiB (MMC3 bank register values #$00-#$77 are valid) yielding a total CHR-ROM size of 480 KiB. If an MMC3 CHR bank register contains a value higher than #$5F/#$77, then the beginning of the last hard-wired outer PRG-ROM bank is mapped into PPU space! The games do not seem to rely on that feature, but it allows me to determine what the outer CHR bank size actually is. Assuming a fixed number of four outer CHR banks, the outer CHR bank size can then be detected by an emulator by simply looking at the number of 8 KiB CHR-ROM banks in the NES header. I don't know how the board actually manages to derive values of #$60 or #$78 from an outer bank register value of #$05, though.
Attached find PCB images,
Edit: See below.
AT least we were able to iron out the issue in civil manner.