I'm currently implementing an MMC5 mapper for my emulator.
According to the specs, the high bit (bit 7) in the MMC5 bank switching registers PRG Bank 0, 1 and 2 ($5114, $5115, $5116) control the ROM/RAM mode of these banks.
By question is: when a bank is set to ROM mode (read only), what should happen if an attempt is made to write to the ROM?
According to the specs, the high bit (bit 7) in the MMC5 bank switching registers PRG Bank 0, 1 and 2 ($5114, $5115, $5116) control the ROM/RAM mode of these banks.
By question is: when a bank is set to ROM mode (read only), what should happen if an attempt is made to write to the ROM?