According to the
wiki page, MMC1 has boards that allow up to 32K of WRAM by abusing the CHR bank select bits.
Should it be extended to allow the third bit, which is normally used for selecting the 256K ROM bank, to also select which 32K of WRAM is mapped in?
Why do you want to specify an extension for a variation that's only hypothetical?
It's one thing to just extend a register that has unused bits, but the bit in question already has two three different functions that emulator authors must disambiguate, and you're asking to overload it with a third fourth. I think this needs some justification (in the form of useful software that requires it).
If you're planning to make something that needs 64k of WRAM, we're already in NES 2.0 territory here; you should just allocate a new mapper in the extended planes for what you need. I don't think we should add complexity to an existing one for this.
Edit: forgot SNROM also reuses the bit for PRG RAM disable.
Also, as an aside, the CHR banking bits are in the reverse order. Bit 3 is the 8k line, and bit 2 is the 16k line, so repurposing bit 4 for the new 32k line might be an unintuitive ordering.
Edit: Was incorrect about this, see below.
rainwarrior wrote:
Also, as an aside, the CHR banking bits are in the reverse order.
I remember you have asserted that that
could be true, and a nice way to simplify emulator logic for SOROM vs SXROM. But have you actually measured on an HVC-SXROM board whether it
is true?
Oh, sorry I did not realize that hadn't been verified.
These are the two MMC1 games with 32k WRAM:
http://bootgod.dyndns.org:7777/search.php?keywords=sxrom&kwtype=pcbEdit: Tried to follow the lines, but the two relevant lines from the MMC1 go underneath the 62256 SRAM so I can't see.
If you want to make a game with huge WRAM on a new board, FME-7 is probably the best bet. It's been
successfully tested with 128K.
Aha, found someone who checked:
http://forums.nesdev.com/viewtopic.php?t=4596So... my assumption was wrong. They're addressed differently for 16k and 32k. I guess that makes sense that they're unrelated, as 16k has to be done with 2 x 8k SRAMs.
So in other words, There are banks 0,1,2,3 on 32K of SRAM, but with 16k of SRAM, it's 0,0,1,1 instead?
Correct. And with the only existing MMC1 board that provides 16K of WRAM, only the second half is battery-backed.
Do you have software that does that yet? (Isn't that how we usually talk about this sort of thing?)
More and more liking the idea of some kind of framework for specifying connectivity…at the least, which registers control which address lines.
It's just that from an emulator author's standpoint, extending WRAM size to 64k is trivial. Just shift the CHR register right 2, then you have 3 bits to select WRAM page. If the size is 32K or smaller, it's mirrored to fill 64K.