I had some branch timing test ROMs mostly written and the recent thread prompted me to finish them. They test branch timing and the edge cases for page crossings that an emulator might get wrong. I also wrote a concise summary of timing (below).
branch_timing_tests.zip
An untaken branch takes 2 clocks. A taken branch takes 3 clocks. A taken branch that crosses a page takes 4 clocks. Page crossing occurs when the high byte of the branch target address is different than the high byte of the address of the next instruction:
branch_timing_tests.zip
An untaken branch takes 2 clocks. A taken branch takes 3 clocks. A taken branch that crosses a page takes 4 clocks. Page crossing occurs when the high byte of the branch target address is different than the high byte of the address of the next instruction:
Code:
branch_target:
...
bne branch_target
next_instruction:
nop
...
branch_target:
...
bne branch_target
next_instruction:
nop
...
branch_target: