opcode $13 (SLO, zero page Y indexed), should take 8 cycles, but I'm getting only 6!
Why???
- Reading the opcode takes 1 cycle;
- decoding the adressing mode takes 2 cycles;
- a SLO takes 4 cycles:
Code:
CPUOP(SLO1)
value = _readvalue(offset); //4th
_writevalue(offset, value); //5th
ASL(value);
writevalue(offset, value); //6th
//ORA0
cpu->A |= value;
SET_SZ_FLAGS(cpu->A);
OPEND
$13 is
slo (dd),y (zero page indirect indexed), not
slo dd,y (zero page indexed). The
dd,y addressing mode exists only for the
ldx,
stx,
lax, and
sax instructions.
Thus
slo ($02),y takes eight cycles:
- Read slo (dd),y opcode
- Read address of pointer
- Read low byte of pointer from dd
- Read high byte of pointer from (dd+1 .mod $100)
- Read old value from partly-formed address
- Read old value from correct address
- Write old value while calculating new value
- Write new value
My reference isn't correct after all...
http://www.oxyron.de/html/opcodes02.htmlUsing this one (old, but gold) now.
http://nesdev.com/6502_cpu.txt
A note at the top of the the oxyron table states that "izy" means (dd),Y. It appears to stand for indirect zero page Y.
SLO always execute the 4th cycle. Normally, this cycle is only executed on page crossing.
What do STA aaaa,X and INC aaaa,X have in common? They always perform the dummy read while adding the index to the address. Likewise, SLO (dd),Y and other unofficial RMW+ALU instructions with (dd),Y are like STA (dd),Y in that they always perform the dummy read.
Dummy reads with the high byte of the address not fixed yet.
The dummy read is always done, even if the address needs no fixing. For example, sta addr, x for x = 0 reads then writes to addr, always.
For pure read instructions using indexed addressing modes (ORA, AND, EOR, ADC, LDA, CMP, SBC, LDX, LDY), the dummy read is skipped if not needed. (Actually, it's the correction read that's skipped once the 6502 realizes that the dummy read was correct.) But for write instructions (STA, STX, STY), read-modify-write instructions (ASL, ROL, LSR, ROR, DEC, INC), and unofficial read-modify-write plus ALU instructions (SLO, RLA, SRE, RRA, DCP, ISC), the dummy read is always performed.
Hmm, a part of my post was left in my head, and not posted
. I wanted to say that all indexed instructions that involve a write always do the dummy read, because it would be wrong to write at a wrong address. Exception is indexed indirect (
OP (zp, x)), because the indexing is done to the indirect address, not to the effective address.