DMA and interrupts

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DMA and interrupts
by 1UP on 2006-04-18 (#12040)
Does anyone know the exact behavior of DMA and interrupts in relation to each other?

All the documentation I've seen says that a DMA read (or write?) keeps the CPU busy for 2 cycles (yeesh!). I would assume that if an interrupt happens during this time, the DMA transfer is scuttled until the interrupt is complete. Or does the interrupt wait until the DMA is complete?

Is this important to know/emulate in the instance when a scanline counter IRQ (or something similar) goes off during a sprite DMA tranfer?

(Yes, I'm one of those people who originally set out to write a "functional equivalence" NES emulator, but then was hit with the hard truth of "functional equivalence == perfect clock-cycle accuracy" in the NES emulation world. I'd assume this is the point where most would-be emulator writers get off this train, but I'm still here.)

by Disch on 2006-04-18 (#12041)
If you're speaking DMC DMA (where it freezes the CPU to fetch a sample byte) -- it's actually a FOUR cycle delay, not one or two as some older docs say. For detailed behavior on when those cycles are stolen, other info needed to get DMC IRQs working properly, and just all around good APU information, I'd recommend reading blargg's APU refernce (as linked to on this page)

As for your main question -- the IRQ wouldn't be able to happen until the CPU is done with its current task... so if an IRQ happens mid DMA (either by DMC or $4014) the earliest the IRQ would occur is after the DMA is complete.

You might also want to browse this thread where I bring up my dismay about what seems like a 1 or 2 cycle delay between when the IRQ is tripped, and when it actually happens. That is at least the case for APU Frame IRQs, but I wonder about some others... (many mapper cpu-cycle based IRQ counters don't work quite right when this delay is put in -- but it seems needed for APU frame IRQs and even MMC3?)

by blargg on 2006-04-18 (#12042)
The only DMA I know about is sprite DMA (triggered by a write to $4014), and APU DMC DMA which steals four CPU clocks. Interrupts are processed when the CPU is clocked, not when the interrupt line itself is asserted, so when the CPU is halted, interrupts will be suspended along with instruction execution.