I'm trying to understand how the address latch works when dealing with PPUSCROLL and PPUADDR.
The wiki states (for SCROLL and ADDR):
My question is this: Since PPUSCROLL and PPUADDR share the same latch, what happens if you mix writes to both addresses?
Example:
Write 0xa to PPUSCROLL, write 0xb to PPUADDR, then write 0xc to PPUSCROLL. What is the value of PPUSCROLL? What is the value of the latch and PPUADDR?
Is it safe to say that the PPUSCROLL and PPUADDR only get set to the value of the latch on their second write, and since the latch is shared, it's whatever the state of the latch is at that point in time? Also what happens when additional writes occur and PPUSTATUS hasn't been read (so the latch hasn't been reset)?
Example:
Write 0xa to PPUSCROLL, write 0xb to PPUSCROLL, write 0xc to PPUSCROLL, what 0xd to PPUSCROLL. What is the value of PPUSCROLL and the latch?
The wiki states (for SCROLL and ADDR):
Quote:
Reading the status register will clear D7 mentioned above and also the address latch used by PPUSCROLL and PPUADDR.
My question is this: Since PPUSCROLL and PPUADDR share the same latch, what happens if you mix writes to both addresses?
Example:
Write 0xa to PPUSCROLL, write 0xb to PPUADDR, then write 0xc to PPUSCROLL. What is the value of PPUSCROLL? What is the value of the latch and PPUADDR?
Is it safe to say that the PPUSCROLL and PPUADDR only get set to the value of the latch on their second write, and since the latch is shared, it's whatever the state of the latch is at that point in time? Also what happens when additional writes occur and PPUSTATUS hasn't been read (so the latch hasn't been reset)?
Example:
Write 0xa to PPUSCROLL, write 0xb to PPUSCROLL, write 0xc to PPUSCROLL, what 0xd to PPUSCROLL. What is the value of PPUSCROLL and the latch?